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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Ishu Brar <patches@brar.si>
Cc: Bjorn Andersson <andersson@kernel.org>,
	 Abel Vesa <abelvesa@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	 Brian Masney <bmasney+clk@redhat.com>,
	Jerome Brunet <jbrunet+clk@baylibre.com>,
	 Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: clock: qcom: Document the SM7250 display clock controller
Date: Mon, 26 Oct 2026 10:35:27 +0100	[thread overview]
Message-ID: <20261026-demonic-polar-python-0abdb0@quoll> (raw)
In-Reply-To: <20261023-dispcc-sm7250-v1-1-07bdefb99801@brar.si>

On Fri, Oct 23, 2026 at 03:48:24PM +0530, Ishu Brar wrote:
> Add the binding and the header with the clock, reset and GDSC indices
> for the display clock controller (DISPCC) of the Qualcomm SM7250 SoC
> (Snapdragon 765/765G/768G).
> 
> The header and the binding are derived from the SM7150 ones: the register
> layout is the same, but the controller takes GPLL0 from the GCC as an
> extra parent and has its own PLL.
> 
> Assisted-by: Claude

Same comments.

Best regards,
Krzysztof


  parent reply	other threads:[~2026-10-26  9:35 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-23 10:18 [PATCH 0/2] clk: qcom: Add SM7250 display clock controller Ishu Brar via B4 Relay
2026-10-23 10:18 ` Ishu Brar
2026-10-23 10:18 ` [PATCH 1/2] dt-bindings: clock: qcom: Document the " Ishu Brar via B4 Relay
2026-10-23 10:18   ` Ishu Brar
2026-10-23 10:38   ` sashiko-bot
2026-10-26  9:35   ` Krzysztof Kozlowski [this message]
2026-10-23 10:18 ` [PATCH 2/2] clk: qcom: Add SM7250 display clock controller driver Ishu Brar via B4 Relay
2026-10-23 10:18   ` Ishu Brar
2026-10-23 10:55   ` sashiko-bot
2026-10-26 11:39   ` Taniya Das

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