From: Robert Marko <robimarko@gmail.com>
To: andersson@kernel.org, abelvesa@kernel.org, sboyd@kernel.org,
bmasney+clk@redhat.com, jbrunet+clk@baylibre.com,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
konradybcio@kernel.org, taniya.das@oss.qualcomm.com,
ansuelsmth@gmail.com, john@phrozen.org,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Robert Marko <robimarko@gmail.com>
Subject: [PATCH v2 3/4] clk: qcom: gcc-ipq8074: Align CMN PLL inputs with binding
Date: Mon, 26 Oct 2026 13:08:14 +0100 [thread overview]
Message-ID: <20261026120920.1667982-3-robimarko@gmail.com> (raw)
In-Reply-To: <20261026120920.1667982-1-robimarko@gmail.com>
The GCC binding names the CMN PLL inputs bias_pll_cc and
bias_pll_nss_noc. Use those names as fw_name so GCC resolves the
clocks through DT references.
Keep the existing .name values as fallbacks for older device trees
without these optional inputs.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
Changes in v2:
- New patch to align GCC parent lookups with the binding input names.
drivers/clk/qcom/gcc-ipq8074.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 1329ea28d703..68c080d49154 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -1132,7 +1132,7 @@ static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
{ .fw_name = "xo", .name = "xo" },
- { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
+ { .fw_name = "bias_pll_nss_noc", .name = "bias_pll_nss_noc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
@@ -1357,7 +1357,7 @@ static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
{ .fw_name = "xo", .name = "xo" },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &nss_crypto_pll.clkr.hw },
@@ -1411,7 +1411,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
@@ -1463,7 +1463,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
@@ -1704,7 +1704,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bia
{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -1774,7 +1774,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bia
{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -1842,7 +1842,7 @@ static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
@@ -1907,7 +1907,7 @@ static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
--
2.56.0
next prev parent reply other threads:[~2026-10-26 12:09 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-26 12:08 [PATCH v2 1/4] clk: qcom: ipq-cmn-pll: Correct IPQ8074 NSS NoC rate Robert Marko
2026-10-26 12:08 ` [PATCH v2 2/4] dt-bindings: clocks: qcom,gcc-ipq8074: Allow CMN PLL bias clocks Robert Marko
2026-10-28 11:35 ` Krzysztof Kozlowski
2026-10-26 12:08 ` Robert Marko [this message]
2026-10-27 10:59 ` [PATCH v2 3/4] clk: qcom: gcc-ipq8074: Align CMN PLL inputs with binding Konrad Dybcio
2026-10-27 11:25 ` Abel Vesa
2026-10-26 12:08 ` [PATCH v2 4/4] arm64: dts: qcom: ipq8074: Add CMN PLL Robert Marko
2026-10-27 10:59 ` Konrad Dybcio
2026-10-27 11:23 ` Abel Vesa
2026-10-27 10:58 ` [PATCH v2 1/4] clk: qcom: ipq-cmn-pll: Correct IPQ8074 NSS NoC rate Konrad Dybcio
2026-10-27 11:24 ` Abel Vesa
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