From: Tom Rini <trini@konsulko.com>
To: Beleswar Padhi <b-padhi@ti.com>
Cc: ilias.apalodimas@linaro.org, afd@ti.com, u-kumar1@ti.com,
u-boot@lists.u-boot-project.org
Subject: Re: [PATCH] arm: omap: Hardcode control_status register for OMAP54xx
Date: Mon, 26 Oct 2026 09:31:38 -0600 [thread overview]
Message-ID: <20261026153138.GD624796@bill-the-cat> (raw)
In-Reply-To: <20261026134848.1733598-1-b-padhi@ti.com>
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On Mon, Oct 26, 2026 at 07:18:48PM +0530, Beleswar Padhi wrote:
> Currently, the control status register address is obtained from the
> ctrl global pointer which points to DDR address 0x8086XXXX. The kernel
> section from the fitImage is loaded to address 0x80008000. So, a larger
> kernel image (~8.4 MB) overwrites the value at the address (0x8086XXXX)
> pointed by the ctrl pointer. This corrupts the (*ctrl) value and CPU
> goes into a data abort when it tries to access the data at addr=(*ctrl)
Why is the ctrl global pointer using a seemingly random point in DDR and
not something in U-Boot itself and so relocated and safe?
--
Tom
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next prev parent reply other threads:[~2026-10-26 15:31 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-26 13:48 [PATCH] arm: omap: Hardcode control_status register for OMAP54xx Beleswar Padhi
2026-10-26 15:31 ` Tom Rini [this message]
2026-10-27 14:16 ` Beleswar Prasad Padhi
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