From: Tony Luck <tony.luck@intel.com>
To: Fenghua Yu <fenghuay@nvidia.com>,
Reinette Chatre <reinette.chatre@intel.com>,
Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>,
Peter Newman <peternewman@google.com>,
James Morse <james.morse@arm.com>,
Babu Moger <babu.moger@amd.com>,
Drew Fustini <dfustini@baylibre.com>,
Dave Martin <Dave.Martin@arm.com>, Chen Yu <yu.c.chen@intel.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
patches@lists.linux.dev, Tony Luck <tony.luck@intel.com>
Subject: [RFC PATCH 3/8] x86/cpuid: Add and use defines for Intel RDT enumeration leaves
Date: Mon, 26 Oct 2026 14:57:13 -0700 [thread overview]
Message-ID: <20261026215718.16810-4-tony.luck@intel.com> (raw)
In-Reply-To: <20261026215718.16810-1-tony.luck@intel.com>
Intel Resource Director Technology (RDT) parameters are enumerated
in four leaves for (monitoring, allocation) * (symmetric, asymmetric).
Add defines for all four leaves.
Update code that hard-codes numerical values for the symmetric leaves.
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
arch/x86/include/asm/cpuid/types.h | 4 ++++
arch/x86/kernel/cpu/resctrl/core.c | 8 ++++----
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index 3d0e611c97ba..9594965a54e7 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -28,9 +28,13 @@ enum cpuid_regs_idx {
#define CPUID_LEAF_MWAIT 0x05
#define CPUID_LEAF_DCA 0x09
#define CPUID_LEAF_XSTATE 0x0d
+#define CPUID_LEAF_RDT_M 0x0f
+#define CPUID_LEAF_RDT_A 0x10
#define CPUID_LEAF_TSC 0x15
#define CPUID_LEAF_FREQ 0x16
#define CPUID_LEAF_TILE 0x1d
+#define CPUID_LEAF_RDT_M_ASYM 0x27
+#define CPUID_LEAF_RDT_A_ASYM 0x28
#define CPUID_RANGE(idx) ((idx) & 0xffff0000)
#define CPUID_RANGE_MAX(idx) (CPUID_RANGE(idx) + 0xffff)
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 709075ffc706..c66ff4cdd84b 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -235,7 +235,7 @@ static __init bool __get_mem_config_intel(struct rdt_resource *r)
union cpuid_0x10_x_edx edx;
u32 ebx, ecx, max_delay;
- cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);
+ cpuid_count(CPUID_LEAF_RDT_A, 3, &eax.full, &ebx, &ecx, &edx.full);
hw_res->num_closid = edx.split.cos_max + 1;
max_delay = eax.split.max_delay + 1;
@@ -357,7 +357,7 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
union cpuid_0x10_x_edx edx;
u32 ebx, default_ctrl;
- cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full);
+ cpuid_count(CPUID_LEAF_RDT_A, idx, &eax.full, &ebx, &ecx.full, &edx.full);
hw_res->num_closid = edx.split.cos_max + 1;
hw_ctrl = kzalloc_obj(*hw_ctrl);
if (!hw_ctrl)
@@ -1196,7 +1196,7 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c)
}
/* will be overridden if occupancy monitoring exists */
- c->x86_cache_max_rmid = cpuid_ebx(0xf);
+ c->x86_cache_max_rmid = cpuid_ebx(CPUID_LEAF_RDT_M);
if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
@@ -1205,7 +1205,7 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c)
u32 eax, ebx, ecx, edx;
/* QoS sub-leaf, EAX=0Fh, ECX=1 */
- cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
+ cpuid_count(CPUID_LEAF_RDT_M, 1, &eax, &ebx, &ecx, &edx);
c->x86_cache_max_rmid = ecx;
c->x86_cache_occ_scale = ebx;
--
2.56.0
next prev parent reply other threads:[~2026-10-26 21:57 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-26 21:57 [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation Tony Luck
2026-10-26 21:57 ` [RFC PATCH 1/8] fs/resctrl: Change UI of "max" file (merge back into earlier patches) Tony Luck
2026-10-26 21:57 ` [RFC PATCH 2/8] x86/resctrl: Add L2CAT quirk for Intel Panther Lake Tony Luck
2026-10-26 21:57 ` Tony Luck [this message]
2026-10-26 21:57 ` [RFC PATCH 4/8] x86/resctrl: Add X86_FEATURE bits for asymmetric L2 Tony Luck
2026-10-26 21:57 ` [RFC PATCH 5/8] x86/resctrl: Refactor rdt_get_cache_alloc_cfg() Tony Luck
2026-10-26 21:57 ` [RFC PATCH 6/8] arm,x86,fs/resctrl: Prepare for asymmetric caches Tony Luck
2026-10-26 21:57 ` [RFC PATCH 7/8] x86/resctrl: Check for and enable asymmetric L2 cache allocation Tony Luck
2026-10-26 21:57 ` [RFC PATCH 8/8] fs/resctrl: Suppress creation of cbm_mask info file on asymmetric systems Tony Luck
2026-10-26 22:30 ` [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation Reinette Chatre
2026-10-27 17:41 ` Luck, Tony
2026-10-27 18:30 ` Reinette Chatre
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261026215718.16810-4-tony.luck@intel.com \
--to=tony.luck@intel.com \
--cc=Dave.Martin@arm.com \
--cc=babu.moger@amd.com \
--cc=dfustini@baylibre.com \
--cc=fenghuay@nvidia.com \
--cc=james.morse@arm.com \
--cc=linux-kernel@vger.kernel.org \
--cc=maciej.wieczor-retman@intel.com \
--cc=patches@lists.linux.dev \
--cc=peternewman@google.com \
--cc=reinette.chatre@intel.com \
--cc=x86@kernel.org \
--cc=yu.c.chen@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.