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d="scan'208";a="4536710" Received: from gfx-coremm-kmd15.iind.intel.com ([10.223.55.8]) by orviesa006.jf.intel.com with ESMTP; 26 Oct 2026 22:13:06 -0700 From: Nareshkumar Gollakoti To: intel-xe@lists.freedesktop.org Cc: tejas.upadhyay@intel.com, Nareshkumar Gollakoti Subject: [PATCH v6 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list Date: Tue, 27 Oct 2026 10:40:22 +0530 Message-ID: <20261027051024.465587-6-naresh.kumar.g@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261027051024.465587-1-naresh.kumar.g@intel.com> References: <20261027051024.465587-1-naresh.kumar.g@intel.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Intel-xe" X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Add ROW_INSTDONE_TDL_GFX, SS_LSC_HDC_IDLE_TDL_GFX and SLICE_ARB_STATUS register definitions and include them in the XeHPG extended GuC capture register list. v2:(Sashiko) - Refactored ROW_INSTDONE_TDL_GFX to ROW_INSTDONE_TDL_GFX - Add SLICE_ARB_STATUS register to xeHP register list - Refactor commit message Signed-off-by: Nareshkumar Gollakoti Reviewed-by: Tejas Upadhyay --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++++ drivers/gpu/drm/xe/xe_guc_capture.c | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index ad8aa6e10e361..f884fc2e38aaf 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -533,6 +533,8 @@ #define PAGE_FLTRPTQ_HEAD XE_REG_MCR(0xcf90) #define PAGE_FLTRPTQ_TAIL XE_REG_MCR(0xcf94) +#define SLICE_ARB_STATUS XE_REG_MCR(0xd814) + #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED) #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0) @@ -597,6 +599,9 @@ #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534) #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31) +#define ROW_INSTDONE_TDL_GFX XE_REG_MCR(0xe580) +#define SS_LSC_HDC_IDLE_TDL_GFX XE_REG_MCR(0xe584) + #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED) #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c index 850e428b0f86b..a8a3271991e2a 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.c +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -376,7 +376,10 @@ static const struct __ext_steer_reg xehpg_extregs[] = { {"SC_INSTDONE", XEHPG_SC_INSTDONE}, {"SC_INSTDONE_EXTRA", XEHPG_SC_INSTDONE_EXTRA}, {"SC_INSTDONE_EXTRA2", XEHPG_SC_INSTDONE_EXTRA2}, - {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT} + {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT}, + {"ROW_INSTDONE_TDL_GFX", ROW_INSTDONE_TDL_GFX}, + {"SS_LSC_HDC_IDLE_TDL_GFX", SS_LSC_HDC_IDLE_TDL_GFX}, + {"SLICE_ARB_STATUS", SLICE_ARB_STATUS} }; static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, -- 2.43.0