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Tue, 27 Oct 2026 07:30:54 -0700 (PDT) Received: from localhost.localdomain ([2606:6d00:159:2900:9872:3600:589:5f3a]) by smtp.gmail.com with ESMTPSA id af79cd13be357-940f0a78c06sm986400885a.35.2026.10.27.07.30.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 27 Oct 2026 07:30:53 -0700 (PDT) From: Marcelo Manzo To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, philmd@oss.qualcomm.com, Sergey Kambalin , Sergey Kambalin , Marcelo Manzo , Jason Wang Subject: [PATCH v6 09/17] hw/net/bcm2838_genet: add GENET register access macros Date: Tue, 27 Oct 2026 10:30:28 -0400 Message-ID: <20261027143036.44973-10-marcelomanzo@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261027143036.44973-1-marcelomanzo@gmail.com> References: <20261027143036.44973-1-marcelomanzo@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=marcelomanzo@gmail.com; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_PASS,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Sergey Kambalin Add offsetof()-based byte-offset macros for the register block layouts added in the previous patches (INTRL0/1, UMAC, TDMA/RDMA and their per-ring registers, HFB filters), used by the MMIO read/write dispatch implemented in the following patches. Part of Sergey Kambalin's original Raspberry Pi 4B PCIe/GENET networking series (patchwork series 829638, posted to qemu-devel in 2024, never merged). Carried forward and completed by Marcelo Manzo. Signed-off-by: Sergey Kambalin Signed-off-by: Marcelo Manzo Reviewed-by: Peter Maydell --- include/hw/net/bcm2838_genet.h | 78 ++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/include/hw/net/bcm2838_genet.h b/include/hw/net/bcm2838_genet.h index 2c3c62a9dd..e0add41aab 100644 --- a/include/hw/net/bcm2838_genet.h +++ b/include/hw/net/bcm2838_genet.h @@ -22,9 +22,87 @@ OBJECT_DECLARE_SIMPLE_TYPE(BCM2838GenetState, BCM2838_GENET) #define BCM2838_GENET_DMA_RING_CNT 17 #define BCM2838_GENET_DMA_RING_DEFAULT (BCM2838_GENET_DMA_RING_CNT - 1) +#define BCM2838_GENET_HFB_FILTER_REGS offsetof(BCM2838GenetRegs, hfb) +#define BCM2838_GENET_HFB_FILTER_REG(reg) (BCM2838_GENET_HFB_FILTER_REGS \ + + offsetof(BCM2838GenetRegsHfb, reg)) #define BCM2838_GENET_HFB_FILTER_CNT 48 #define BCM2838_GENET_HFB_FILTER_SIZE 128 +#define BCM2838_GENET_INTRL0_REG(reg) (offsetof(BCM2838GenetRegs, intrl0) \ + + offsetof(BCM2838GenetRegsIntrl0, reg)) +#define BCM2838_GENET_INTRL0_SET BCM2838_GENET_INTRL0_REG(set) +#define BCM2838_GENET_INTRL0_CLEAR BCM2838_GENET_INTRL0_REG(clear) +#define BCM2838_GENET_INTRL0_MASK_SET BCM2838_GENET_INTRL0_REG(mask_set) +#define BCM2838_GENET_INTRL0_MASK_CLEAR BCM2838_GENET_INTRL0_REG(mask_clear) + +#define BCM2838_GENET_INTRL1_REG(reg) (offsetof(BCM2838GenetRegs, intrl1) \ + + offsetof(BCM2838GenetRegsIntrl1, reg)) +#define BCM2838_GENET_INTRL1_SET BCM2838_GENET_INTRL1_REG(set) +#define BCM2838_GENET_INTRL1_CLEAR BCM2838_GENET_INTRL1_REG(clear) +#define BCM2838_GENET_INTRL1_MASK_SET BCM2838_GENET_INTRL1_REG(mask_set) +#define BCM2838_GENET_INTRL1_MASK_CLEAR BCM2838_GENET_INTRL1_REG(mask_clear) + +#define BCM2838_GENET_UMAC_REG(reg) (offsetof(BCM2838GenetRegs, umac) \ + + offsetof(BCM2838GenetRegsUmac, reg)) +#define BCM2838_GENET_UMAC_CMD BCM2838_GENET_UMAC_REG(cmd) +#define BCM2838_GENET_UMAC_MAC0 BCM2838_GENET_UMAC_REG(mac0) +#define BCM2838_GENET_UMAC_MAC1 BCM2838_GENET_UMAC_REG(mac1) +#define BCM2838_GENET_UMAC_MDIO_CMD BCM2838_GENET_UMAC_REG(mdio_cmd) + +#define BCM2838_GENET_TDMA_REGS offsetof(BCM2838GenetRegs, tdma) +#define BCM2838_GENET_TDMA_REG(reg) (BCM2838_GENET_TDMA_REGS \ + + offsetof(BCM2838GenetRegsTdma, reg)) +#define BCM2838_GENET_TDMA_RINGS BCM2838_GENET_TDMA_REG(rings) +#define BCM2838_GENET_TDMA_RING_CFG BCM2838_GENET_TDMA_REG(ring_cfg) +#define BCM2838_GENET_TDMA_CTRL BCM2838_GENET_TDMA_REG(ctrl) +#define BCM2838_GENET_TDMA_STATUS BCM2838_GENET_TDMA_REG(status) + +#define BCM2838_GENET_RDMA_REGS offsetof(BCM2838GenetRegs, rdma) +#define BCM2838_GENET_RDMA_REG(reg) (BCM2838_GENET_RDMA_REGS \ + + offsetof(BCM2838GenetRegsRdma, reg)) +#define BCM2838_GENET_RDMA_RINGS BCM2838_GENET_RDMA_REG(rings) +#define BCM2838_GENET_RDMA_RING_CFG BCM2838_GENET_RDMA_REG(ring_cfg) +#define BCM2838_GENET_RDMA_CTRL BCM2838_GENET_RDMA_REG(ctrl) +#define BCM2838_GENET_RDMA_STATUS BCM2838_GENET_RDMA_REG(status) + +#define BCM2838_GENET_TRING_REG(reg) offsetof(BCM2838GenetTdmaRing, reg) +#define BCM2838_GENET_TRING_WRITE_PTR BCM2838_GENET_TRING_REG(write_ptr) +#define BCM2838_GENET_TRING_WRITE_PTR_HI BCM2838_GENET_TRING_REG(write_ptr_hi) +#define BCM2838_GENET_TRING_PROD_INDEX BCM2838_GENET_TRING_REG(prod_index) +#define BCM2838_GENET_TRING_CONS_INDEX BCM2838_GENET_TRING_REG(cons_index) +#define BCM2838_GENET_TRING_RING_BUF_SIZE BCM2838_GENET_TRING_REG(ring_buf_size) +#define BCM2838_GENET_TRING_RING_START_ADDR BCM2838_GENET_TRING_REG(start_addr) +#define BCM2838_GENET_TRING_RING_START_ADDR_HI BCM2838_GENET_TRING_REG(start_addr_hi) +#define BCM2838_GENET_TRING_RING_END_ADDR BCM2838_GENET_TRING_REG(end_addr) +#define BCM2838_GENET_TRING_RING_END_ADDR_HI BCM2838_GENET_TRING_REG(end_addr_hi) +#define BCM2838_GENET_TRING_RING_MBUF_DONE_TRESH BCM2838_GENET_TRING_REG(mbuf_done_tresh) +#define BCM2838_GENET_TRING_RING_FLOW_PERIOD BCM2838_GENET_TRING_REG(flow_period) +#define BCM2838_GENET_TRING_RING_READ_PTR BCM2838_GENET_TRING_REG(read_ptr) +#define BCM2838_GENET_TRING_RING_READ_PTR_HI BCM2838_GENET_TRING_REG(read_ptr_hi) + +#define BCM2838_GENET_RRING_REG(reg) offsetof(BCM2838GenetRdmaRing, reg) +#define BCM2838_GENET_RRING_WRITE_PTR BCM2838_GENET_RRING_REG(write_ptr) +#define BCM2838_GENET_RRING_WRITE_PTR_HI BCM2838_GENET_RRING_REG(write_ptr_hi) +#define BCM2838_GENET_RRING_PROD_INDEX BCM2838_GENET_RRING_REG(prod_index) +#define BCM2838_GENET_RRING_CONS_INDEX BCM2838_GENET_RRING_REG(cons_index) +#define BCM2838_GENET_RRING_RING_BUF_SIZE BCM2838_GENET_RRING_REG(ring_buf_size) +#define BCM2838_GENET_RRING_RING_START_ADDR BCM2838_GENET_RRING_REG(start_addr) +#define BCM2838_GENET_RRING_RING_START_ADDR_HI BCM2838_GENET_RRING_REG(start_addr_hi) +#define BCM2838_GENET_RRING_RING_END_ADDR BCM2838_GENET_RRING_REG(end_addr) +#define BCM2838_GENET_RRING_RING_END_ADDR_HI BCM2838_GENET_RRING_REG(end_addr_hi) +#define BCM2838_GENET_RRING_RING_MBUF_DONE_TRESH BCM2838_GENET_RRING_REG(mbuf_done_tresh) +#define BCM2838_GENET_RRING_RING_XON_XOFF_TRESH BCM2838_GENET_RRING_REG(xon_xoff_tresh) +#define BCM2838_GENET_RRING_RING_READ_PTR BCM2838_GENET_RRING_REG(read_ptr) +#define BCM2838_GENET_RRING_RING_READ_PTR_HI BCM2838_GENET_RRING_REG(read_ptr_hi) + + +#define BCM2838_GENET_PHY_REG(reg) (offsetof(BCM2838GenetPhyRegs, reg) / 2) +#define BCM2838_GENET_PHY_BMCR BCM2838_GENET_PHY_REG(bmcr) +#define BCM2838_GENET_PHY_AUX_CTL BCM2838_GENET_PHY_REG(aux_ctl) +#define BCM2838_GENET_PHY_SHD BCM2838_GENET_PHY_REG(shd) +#define BCM2838_GENET_EXP_DATA BCM2838_GENET_PHY_REG(exp_data) +#define BCM2838_GENET_EXP_SEL BCM2838_GENET_PHY_REG(exp_ctrl) + #define BCM2838_GENET_PHY_AUX_CTL_MISC 0x7 #define BCM2838_GENET_PHY_AUX_CTL_REGS_SIZE 8 -- 2.55.0