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[82.67.153.177]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a94f5311bdsm2985205e9.5.2026.10.27.12.28.34 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 27 Oct 2026 12:28:34 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 43/59] hw/net/imx_fec: Trace with QOM path where easily possible Date: Tue, 27 Oct 2026 20:23:24 +0100 Message-ID: <20261027192341.9197-44-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261027192341.9197-1-philmd@oss.qualcomm.com> References: <20261027192341.9197-1-philmd@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI3MDA3OCBTYWx0ZWRfXyWCPjaoAAvCx OhLhM28puRjfmBR3bBBOAsshj1lVQbz/xy0Nr2p2e910pkQmxwQ4IeENE7tK7WxWwXou8Tioime 2F7SVpJO+UssdvCtvCLCaiz+pwBGIx8= X-Proofpoint-ORIG-GUID: K_3MbQLDEBpbCqn8J3AXBf3I9uKClzhb X-Proofpoint-GUID: K_3MbQLDEBpbCqn8J3AXBf3I9uKClzhb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI3MDA3OCBTYWx0ZWRfXzz1HoDKdEoCV EYPvjxZg3IsfKq939gXHPU88fL8xHKr2A5Vyz+fN1jszN/6ZkEpIC6y42Vl1pJE4+wxM6jash+V dsCSxUegj9SYLLJYcnBx/c0yKCjIP/Tq4jEP+Dy5K7JqRIHBtxrrxwy1Nl7efg0bQdXdoXoQKBH daqFqqMKrw/cMugWqgwWf2uaIApQM9J2EDIgDKDzOL8w6ZNbos9mGmxuaVWKCs587sRjnFAPRSQ FEvw07Wsb0wwb+/9ztK8tglvxfO2cPqucvwN+svz2TRoDCL0YTdiABJOelUIo6WQVmY62NnHol2 O2k30bRQlvfSkqC3UnyoXLNDErOzy5mP7zWp1FzBB/NqgIQ0uOctEEDArNijTKGy7rfofmq71l5 MayEefThFiZUeaQNYErUpLXbHnCrPcRLy0OOC/CBU9JZHJ2v1NCh6KMXbjBoPXgAvwTOz1U6JtL 6Q5abEXA2MK1T6UOKcw== X-Authority-Analysis: v=2.4 cv=UOFIjyfy c=1 sm=1 tr=0 ts=6ae0fb64 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=nz36NW0qrpeEijYxj/H2Ew==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=DJJ0lQ6uop2uk4lV2pUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-27_05,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610270078 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, KHOP_DYNAMIC=0.001, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Bernhard Beschow Some i.MX SoCs have multiple i.MX network IP blocks. Allow to distinguish them via their QOM path when tracing. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20260921214710.29422-41-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/net/imx_fec.c | 28 +++++++++++++++------------- hw/net/trace-events | 24 ++++++++++++------------ 2 files changed, 27 insertions(+), 25 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index c177b7ff2b7b..fb8bcd52d203 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -248,7 +248,7 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) if (s->phy_consumer && phy == s->phy_consumer->phy_num) { s = s->phy_consumer; } else { - trace_imx_phy_read_num(phy, s->phy_num); + trace_imx_phy_read_num(DEVICE(s)->canonical_path, phy, s->phy_num); return 0xffff; } } @@ -270,7 +270,7 @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) if (s->phy_consumer && phy == s->phy_consumer->phy_num) { s = s->phy_consumer; } else { - trace_imx_phy_write_num(phy, s->phy_num); + trace_imx_phy_write_num(DEVICE(s)->canonical_path, phy, s->phy_num); return; } } @@ -364,7 +364,7 @@ static void imx_fec_do_tx(IMXFECState *s) if ((bd.flags & ENET_BD_R) == 0) { /* Run out of descriptors to transmit. */ - trace_imx_eth_tx_bd_busy(); + trace_imx_eth_tx_bd_busy(DEVICE(s)->canonical_path); break; } @@ -446,7 +446,7 @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index) if ((bd.flags & ENET_BD_R) == 0) { /* Run out of descriptors to transmit. */ - trace_imx_eth_tx_bd_busy(); + trace_imx_eth_tx_bd_busy(DEVICE(s)->canonical_path); break; } @@ -521,7 +521,7 @@ static void imx_eth_enable_rx(IMXFECState *s, bool flush) s->regs[ENET_RDAR] = (bd.flags & ENET_BD_E) ? ENET_RDAR_RDAR : 0; if (!s->regs[ENET_RDAR]) { - trace_imx_eth_rx_bd_full(); + trace_imx_eth_rx_bd_full(DEVICE(s)->canonical_path); } else if (flush) { qemu_flush_queued_packets(qemu_get_queue(s->nic)); } @@ -659,7 +659,8 @@ static uint64_t imx_eth_read(void *opaque, hwaddr offset, unsigned size) break; } - trace_imx_eth_read(index, imx_eth_reg_name(s, index), value); + trace_imx_eth_read(DEVICE(s)->canonical_path, index, + imx_eth_reg_name(s, index), value); return value; } @@ -767,7 +768,8 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s); uint32_t index = offset >> 2; - trace_imx_eth_write(index, imx_eth_reg_name(s, index), value); + trace_imx_eth_write(DEVICE(s)->canonical_path, index, + imx_eth_reg_name(s, index), value); switch (index) { case ENET_EIR: @@ -951,7 +953,7 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, unsigned int buf_len; size_t size = len; - trace_imx_fec_receive(size); + trace_imx_fec_receive(DEVICE(s)->canonical_path, size); if (!s->regs[ENET_RDAR]) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n", @@ -993,7 +995,7 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, bd.length = buf_len; size -= buf_len; - trace_imx_fec_receive_len(addr, bd.length); + trace_imx_fec_receive_len(DEVICE(s)->canonical_path, addr, bd.length); /* The last 4 bytes are the CRC. */ if (size < 4) { @@ -1013,7 +1015,7 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, /* Last buffer in frame. */ bd.flags |= flags | ENET_BD_L; - trace_imx_fec_receive_last(bd.flags); + trace_imx_fec_receive_last(DEVICE(s)->canonical_path, bd.flags); s->regs[ENET_EIR] |= ENET_INT_RXF; } else { @@ -1047,7 +1049,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size = len; bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; - trace_imx_enet_receive(size); + trace_imx_enet_receive(DEVICE(s)->canonical_path, size); if (!s->regs[ENET_RDAR]) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n", @@ -1093,7 +1095,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, bd.length = buf_len; size -= buf_len; - trace_imx_enet_receive_len(addr, bd.length); + trace_imx_enet_receive_len(DEVICE(s)->canonical_path, addr, bd.length); /* The last 4 bytes are the CRC. */ if (size < 4) { @@ -1131,7 +1133,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, /* Last buffer in frame. */ bd.flags |= flags | ENET_BD_L; - trace_imx_enet_receive_last(bd.flags); + trace_imx_enet_receive_last(DEVICE(s)->canonical_path, bd.flags); /* Indicate that we've updated the last buffer descriptor. */ bd.last_buffer = ENET_BD_BDU; diff --git a/hw/net/trace-events b/hw/net/trace-events index 001a20b0e2ac..81af808044e1 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -444,20 +444,20 @@ i82596_ca_init(uint32_t scb, uint8_t mode, uint32_t base) "CA: Init - SCB=0x%08x i82596_ioport_write(uint32_t addr, uint32_t val) "IO write addr=0x%08x val=0x%08x" # imx_fec.c -imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" -imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" +imx_phy_read_num(const char *path, int phy, int configured) "%s: read request from unconfigured phy %d (configured %d)" +imx_phy_write_num(const char *path, int phy, int configured) "%s: write request to unconfigured phy %d (configured %d)" imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" -imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" -imx_eth_rx_bd_full(void) "RX buffer is full" -imx_eth_read(int reg, const char *reg_name, uint32_t value) "reg[%d:%s] => 0x%08"PRIx32 -imx_eth_write(int reg, const char *reg_name, uint64_t value) "reg[%d:%s] <= 0x%08"PRIx64 -imx_fec_receive(size_t size) "len %zu" -imx_fec_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" -imx_fec_receive_last(int last) "rx frame flags 0x%04x" -imx_enet_receive(size_t size) "len %zu" -imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" -imx_enet_receive_last(int last) "rx frame flags 0x%04x" +imx_eth_tx_bd_busy(const char *path) "%s: tx_bd ran out of descriptors to transmit" +imx_eth_rx_bd_full(const char *path) "%s: RX buffer is full" +imx_eth_read(const char *path, int reg, const char *reg_name, uint32_t value) "%s: reg[%d:%s] => 0x%08"PRIx32 +imx_eth_write(const char *path, int reg, const char *reg_name, uint64_t value) "%s: reg[%d:%s] <= 0x%08"PRIx64 +imx_fec_receive(const char *path, size_t size) "%s: len %zu" +imx_fec_receive_len(const char *path, uint64_t addr, int len) "%s: rx_bd 0x%"PRIx64" length %d" +imx_fec_receive_last(const char *path, int last) "%s: rx frame flags 0x%04x" +imx_enet_receive(const char *path, size_t size) "%s: len %zu" +imx_enet_receive_len(const char *path, uint64_t addr, int len) "%s, rx_bd 0x%"PRIx64" length %d" +imx_enet_receive_last(const char *path, int last) "%s: rx frame flags 0x%04x" # npcm7xx_emc.c npcm7xx_emc_reset(int emc_num) "Resetting emc%d" -- 2.55.0