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Korinsky" , Helge Deller Subject: [PATCH 2/8] target/hppa: Use 15 bit protection IDs on PA1.1 CPUs Date: Tue, 27 Oct 2026 22:52:03 +0100 Message-ID: <20261027215209.21150-3-deller@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20261027215209.21150-1-deller@kernel.org> References: <20261027215209.21150-1-deller@kernel.org> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2600:3c04:e001:324:0:1991:8:25; envelope-from=deller@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Keith Monahan HP-UX 9.05 only supports 15-bit protection IDs and gets a protection fault on its own interrupt stack when allowing 18-bits. Since the architecture manual states that if smaller than 18-bit access IDs are physically implemented in the CPU, only the appropriate number of rightmost bits of GR[r]{13..30} are stored in the TLB. PA7100 and PA7100LC only support 15 bit protection IDs, so use this amount of bits here. Signed-off-by: Keith Monahan Signed-off-by: Helge Deller --- target/hppa/mem_helper.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index a5da0bc851..7a316f59ea 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -538,7 +538,15 @@ void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong reg) static void set_access_bits_pa11(CPUHPPAState *env, HPPATLBEntry *ent, target_ulong reg) { - ent->access_id = extract32(reg, 1, 18); + /* + * The architecture manual states that if smaller than 18-bit access IDs + * are physically implemented in the CPU, only the appropriate number of + * rightmost bits of GR[r]{13..30} are stored in the TLB. Older parisc + * chips (PCXS, PCXT, PCXL, PCXL2) only support 15 bit protection IDs. + * PCXT' (pa7200) has 18 bit protection IDs, but only 16 bit spaceids. + * We currently emulate PA7100 and PA7100LC CPUs, so use 15 bits here. + */ + ent->access_id = extract32(reg, 1, 15); /* 15-bit PA1.1 PIDs */ ent->u = extract32(reg, 19, 1); ent->ar_pl2 = extract32(reg, 20, 2); ent->ar_pl1 = extract32(reg, 22, 2); -- 2.54.0