From: Alex Hung <alex.hung@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
James Lin <PingLei.Lin@amd.com>,
Chenyu Chen <Chen-Yu.Chen@amd.com>,
Ilya Bakoulin <Ilya.Bakoulin@amd.com>,
Wenjing Liu <wenjing.liu@amd.com>
Subject: [PATCH 06/28] drm/amd/display: Adjust DSC slice calc. policy
Date: Tue, 27 Oct 2026 17:17:02 -0600 [thread overview]
Message-ID: <20261027232005.2879750-7-alex.hung@amd.com> (raw)
In-Reply-To: <20261027232005.2879750-1-alex.hung@amd.com>
From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
[WHY & HOW]
Need to adjust the DSC slice calculation to reflect the policy change
where given a 1-slice config limit:
- Throughput per slice is limited to the 1-slice limit up to 4 slices
- Throughput per slice is tied to DSC encoder caps for 8+ slices
This is needed to avoid cases where some DSC config can end up exceeding
the 1-slice throughput limit either by itself or with dynamic ODM.
Cc: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
.../display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 31 ++++++++++++++++++-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 24 +++++++++++++-
.../drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c | 1 +
drivers/gpu/drm/amd/display/dc/dsc/dsc.h | 1 +
4 files changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
index 29082b186134..1c8daa7d46a1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
@@ -1778,6 +1778,35 @@ static void dcn60_execute_clk_mgr_block_sequence_bls(struct clk_mgr *clk_mgr_bas
dcn60_execute_block_sequence(clk_mgr_base, clk_mgr60->num_block_sequence_steps);
}
+static unsigned int dcn60_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+ unsigned int num_clk_levels;
+
+ switch (clk_type) {
+ case CLK_TYPE_DISPCLK:
+ num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;
+ return dcn60_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK) ?
+ clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 :
+ clk_mgr->base.boot_snapshot.dispclk;
+ case CLK_TYPE_DPPCLK:
+ num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;
+ return dcn60_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DPPCLK) ?
+ clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 :
+ clk_mgr->base.boot_snapshot.dppclk;
+ case CLK_TYPE_DSCCLK:
+ num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;
+ return dcn60_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK) ?
+ clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 6 :
+ clk_mgr->base.boot_snapshot.dispclk / 6;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
static struct clk_mgr_funcs dcn60_funcs = {
.get_dp_ref_clk_frequency = dcn10_get_dp_ref_freq_khz,
.get_dtb_ref_clk_frequency = dcn60_get_dtb_ref_freq_khz,
@@ -1790,7 +1819,7 @@ static struct clk_mgr_funcs dcn60_funcs = {
.enable_pme_wa = dcn60_enable_pme_wa,
.is_smu_present = dcn60_is_smu_present,
.get_dispclk_from_dentist = NULL,
- .get_max_clock_khz = dcn401_get_max_clock_khz,
+ .get_max_clock_khz = dcn60_get_max_clock_khz,
.override_memory_bandwidth_request = dcn60_override_memory_bandwidth_request,
.get_requested_memory_qos = dcn60_get_requested_memory_qos,
.set_idle_power_optimizations = dcn60_set_idle_power_optimizations,
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index febb6af43827..45ef1f745c7d 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -1057,7 +1057,7 @@ static void build_dsc_enc_caps(
unsigned int max_dscclk_khz;
unsigned int num_dsc;
unsigned int max_odm_combine_factor;
- struct dsc_enc_caps single_dsc_enc_caps;
+ struct dsc_enc_caps single_dsc_enc_caps = {0};
struct dc *dc;
@@ -1082,6 +1082,7 @@ static void build_dsc_enc_caps(
dsc_enc_caps->bpp_increment_div = single_dsc_enc_caps.bpp_increment_div;
dsc_enc_caps->color_formats.raw = single_dsc_enc_caps.color_formats.raw;
dsc_enc_caps->color_depth.raw = single_dsc_enc_caps.color_depth.raw;
+ dsc_enc_caps->single_slice_config_throughput_mps = single_dsc_enc_caps.single_slice_config_throughput_mps;
/* expand per DSC capabilities to global */
max_odm_combine_factor = dc->caps.max_odm_combine_factor;
@@ -1873,6 +1874,27 @@ static bool setup_dsc_config(
min_slices_h = inc_num_slices(dsc_common_caps.slice_caps, min_slices_h);
}
+ /* Increase minimum slice count to meet DSC encoder clock and dynamic ODM limitations.
+ *
+ * Make sure that dynamic ODM can't create a config where there is 1 slice per ODM pipe and
+ * the required 1-slice throughput exceeds single_slice_config_throughput_mps.
+ * E.g. a 2-to-1 ODM config with 4 total slices transitioning to 4-to-1 ODM.
+ *
+ * Also prevent a single-slice non-ODM config where 1-slice throughput exceeds
+ * single_slice_config_throughput_mps.
+ */
+ while (min_slices_h <= max_slices_h && dsc_enc_caps->single_slice_config_throughput_mps) {
+ int pix_clk_per_slice_khz = dsc_div_by_10_round_up(timing->pix_clk_100hz) / min_slices_h;
+ /* Don't care about this condition if there is a minimum of 2 slices per ODM at max split */
+ if (min_slices_h > 4)
+ break;
+ if (min_slices_h <= 4 &&
+ pix_clk_per_slice_khz <= (dsc_enc_caps->single_slice_config_throughput_mps * 1000))
+ break;
+
+ min_slices_h = inc_num_slices(dsc_common_caps.slice_caps, min_slices_h);
+ }
+
/* increase minimum slice count to meet divisibility requirements */
while (pic_width % min_slices_h != 0 && min_slices_h <= max_slices_h) {
min_slices_h = inc_num_slices(dsc_common_caps.slice_caps, min_slices_h);
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c
index 91ec525b11d0..a349a416240d 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c
@@ -458,6 +458,7 @@ void dsc60_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int m
dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
dsc_enc_caps->max_total_throughput_mps = max_dscclk_khz * 3 / 1000;
+ dsc_enc_caps->single_slice_config_throughput_mps = 340;
dsc_enc_caps->max_slice_width = 5760; /* (including 64 overlap pixels for eDP MSO mode) */
dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h
index cb7b0b1d8686..4f58d0ddbf22 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h
@@ -100,6 +100,7 @@ struct dsc_enc_caps {
union dsc_color_formats color_formats;
union dsc_color_depth color_depth;
int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */
+ int32_t single_slice_config_throughput_mps;
int32_t max_slice_width;
uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
bool is_frl;
--
2.53.0
next prev parent reply other threads:[~2026-10-27 23:22 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-27 23:16 [PATCH 00/28] DC Patches Oct 27, 2026 Alex Hung
2026-10-27 23:16 ` [PATCH 01/28] drm/amd/display: Use DCN6 driver_if for PPCLK_e enum Alex Hung
2026-10-27 23:16 ` [PATCH 02/28] drm/amd/display: Allow bypassing link_off_frame_count check for replay debug mode Alex Hung
2026-10-27 23:16 ` [PATCH 03/28] drm/amd/display: Clarify endianness error Alex Hung
2026-10-27 23:17 ` [PATCH 04/28] drm/amd/display: Add visual confirm full viewport debug option Alex Hung
2026-10-27 23:17 ` [PATCH 05/28] drm/amd/display: Remove DCN401 RDPCS PHY state reads Alex Hung
2026-10-27 23:17 ` Alex Hung [this message]
2026-10-27 23:17 ` [PATCH 07/28] drm/amd/display: Configure alternate-channel apertures Alex Hung
2026-10-27 23:17 ` [PATCH 08/28] drm/amd/display: Avoid closing unowned DDC pins Alex Hung
2026-10-27 23:17 ` [PATCH 09/28] drm/amd/display: Support replay frame update interval Alex Hung
2026-10-27 23:17 ` [PATCH 10/28] drm/amd/display: Indicate wait_resp based on FAMS even in disable path Alex Hung
2026-10-27 23:17 ` [PATCH 11/28] drm/amd/display: Update Rounding For VM stage groups Alex Hung
2026-10-27 23:17 ` [PATCH 12/28] drm/amd/display: Fix unadvertised mode detection Alex Hung
2026-10-27 23:17 ` [PATCH 13/28] drm/amd/display: Parameterize FCLK/PPT/Temp Read P-State Optimizer Alex Hung
2026-10-27 23:17 ` [PATCH 14/28] drm/amd/display: Reset DET of HUBPs without a plane before outstanding updates Alex Hung
2026-10-27 23:17 ` [PATCH 15/28] drm/amd/display: Decouple FAMS2 config update from dc/dc_state and add BLS opcode Alex Hung
2026-10-27 23:17 ` [PATCH 16/28] drm/amd/display: Add missing OTG_CRC1 reg/mask entries for DCN3.1.4 Alex Hung
2026-10-27 23:17 ` [PATCH 17/28] drm/amd/display: Add missing OTG_CRC1 reg/mask entries for DCN3.1.2 Alex Hung
2026-10-27 23:17 ` [PATCH 18/28] drm/amd/display: Skip dsc sequence for stream if dpms off Alex Hung
2026-10-27 23:17 ` [PATCH 19/28] drm/amd/display: Add debugfs override for HDMI VRR Alex Hung
2026-10-27 23:17 ` [PATCH 20/28] drm/amd/display: Enable immediate restore for FAMS on DCN6 Alex Hung
2026-10-27 23:17 ` [PATCH 21/28] drm/amd/display: Expand DSCCLK support check Alex Hung
2026-10-27 23:17 ` [PATCH 22/28] drm/amd/display: Add more backlight Kunit tests Alex Hung
2026-10-27 23:17 ` [PATCH 23/28] drm/amd/display: Add more color KUnit tests Alex Hung
2026-10-27 23:17 ` [PATCH 24/28] drm/amd/display: Add more CRC " Alex Hung
2026-10-27 23:17 ` [PATCH 25/28] drm/amd/display: Add more connector " Alex Hung
2026-10-27 23:17 ` [PATCH 26/28] drm/amd/display: Update alt shared lib to use dynamic state Alex Hung
2026-10-27 23:17 ` [PATCH 27/28] drm/amd/display: [FW Promotion] Release 0.1.82.0 Alex Hung
2026-10-27 23:17 ` [PATCH 28/28] drm/amd/display: Promote DC to 3.2.405 Alex Hung
2026-10-30 15:42 ` [PATCH 00/28] DC Patches Oct 27, 2026 Leo Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261027232005.2879750-7-alex.hung@amd.com \
--to=alex.hung@amd.com \
--cc=Chen-Yu.Chen@amd.com \
--cc=Ilya.Bakoulin@amd.com \
--cc=PingLei.Lin@amd.com \
--cc=Ray.Wu@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=aurabindo.pillai@amd.com \
--cc=chiahsuan.chung@amd.com \
--cc=daniel.wheeler@amd.com \
--cc=harry.wentland@amd.com \
--cc=ivan.lipski@amd.com \
--cc=jerry.zuo@amd.com \
--cc=roman.li@amd.com \
--cc=sunpeng.li@amd.com \
--cc=wayne.lin@amd.com \
--cc=wenjing.liu@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.