[PATCH v2 2/2] tests/intel/xe_prefetch_fault: remove explicit regioning and channel offsets

[Andrzej Hajda <andrzej.hajda@intel.com>]

There is no need to specify regioning and channel offset in
most cases. Default genisa values are:
- <0;1,0> for source region,
- <1> for destination region,
- M0 for channel offset.
The patch also enforces common formating for all asms:
- preprocessor instructions and predicates start from beginning of the line,
- instruction mnemonic starts from 1st tab,
- exec size follows mnemonic after one space,
- flag modifiers, if any, are placed after exec size,
- arguments starts from 3rd tab,
- no tabs/multi-spaces between/after arguments

The changes do not affect produced binary code.

Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
 tests/intel/xe_prefetch_fault.c                   | 16 ++++++++--------
 tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c |  2 +-
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/tests/intel/xe_prefetch_fault.c b/tests/intel/xe_prefetch_fault.c
index ce741d5b229b..91c3797c3219 100644
--- a/tests/intel/xe_prefetch_fault.c
+++ b/tests/intel/xe_prefetch_fault.c
@@ -54,11 +54,11 @@ static void gpgpu_shader__prefetch_fault(struct gpgpu_shader *shdr,
 #if GFX_VER >= 3500
 L0:
 // Set base address with scalar register
-(W)	mov (1)		s0.0<1>:ud		ARG(0):ud
-(W)	mov (1)		s0.1<1>:ud		ARG(1):ud
+(W)	mov (1)		s0.0:ud ARG(0):ud
+(W)	mov (1)		s0.1:ud ARG(1):ud
 
 // A64 offset
-(W)	mov (8)		r30.0<1>:uq		0x0:uq
+(W)	mov (8)		r30.0:uq 0x0:uq
 
 // efficient 64bit Read with cached L1, cached L2 and cached L3
 // sendg ugm load with SBID 3
@@ -75,7 +75,7 @@ L0:
 //      [9:7] Vector Size: 0 (Vector length 1)
 //      [5:0] Opcode: 0 (Load)
 // Prefetch operations are implemented using a NULL destination register.
-(W)	sendg.ugm (1|M0)	null	r30:1	null:0	s0.0	0x99C00	{A@1,$5}
+(W)	sendg.ugm (1)	null r30:1 null:0 s0.0 0x99C00 {A@1,$5}
 
 #endif
 	)", lower_32_bits(addr), upper_32_bits(addr));
@@ -149,16 +149,16 @@ static struct gpgpu_shader *get_l2_prefetch_shader(int fd)
 #if GFX_VER >= 3500
 L0:
 // Set base address with scalar register
-(W)   mov (1)                s0.0<1>:ud                         ARG(0):ud
-(W)   mov (1)                s0.1<1>:ud                         ARG(1):ud
+(W)	mov (1)		s0.0:ud ARG(0):ud
+(W)	mov (1)		s0.1:ud ARG(1):ud
 
 // A64 offset
-(W)   mov (8)                r30.0<1>:uq                       0x0:uq
+(W)	mov (8)		r30.0:uq 0x0:uq
 
 // Prefetch operations are implemented using a NULL destination register.
 // L1 uncached forces the prefetch to bypass LSC, making L2 the fault source.
 // load.ugm.d64t.a64.uc.ca.uc [src0]
-(W)   sendg.ugm (1)          null         r30:1      null:0     s0.0        0x49C00
+(W)	sendg.ugm (1)	null r30:1 null:0 s0.0 0x49C00
 #endif
 	)", lower_32_bits(addr), upper_32_bits(addr));
 
diff --git a/tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c b/tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c
index 5d387aa08f1b..a4d9f8c71c04 100644
--- a/tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c
+++ b/tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c
@@ -3,7 +3,7 @@
 
 #include "gpgpu_shader.h"
 
-#define MD5_SUM_IGA64_ASMS 712da12709dd4ebfeffc82119c37c556
+#define MD5_SUM_IGA64_ASMS 814fcd58b85fe7295c5017059f3db49e
 
 struct iga64_template const iga64_code_xe_l2_prefetch_fault_prefetch[] = {
 	{ .gfx_ver = 3500, .size = 28, .code = (const uint32_t []) {

-- 
2.55.0