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Wed, 28 Oct 2026 02:31:57 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Kane Chen , Alistair Francis , Kevin Wolf , Hanna Reitz , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: Jamin Lin , Troy Lee , =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= Subject: [PATCH v2 02/13] hw/ssi/aspeed_smc: Fix AST2700 DMA flash address mask Thread-Topic: [PATCH v2 02/13] hw/ssi/aspeed_smc: Fix AST2700 DMA flash address mask Thread-Index: AQHdZoSA2xt3qMXuM0emT3ls4Oz45Q== Date: Wed, 28 Oct 2026 02:31:57 +0000 Message-ID: <20261028023154.48395-3-jamin_lin@aspeedtech.com> References: <20261028023154.48395-1-jamin_lin@aspeedtech.com> In-Reply-To: <20261028023154.48395-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Archived-By: MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SEZPR06MB7362.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 60cbd52a-51a4-4cdf-9e6a-08df349ba31b X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Oct 2026 02:31:57.0839 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Yg3PVM7ZyatOS7UtaQ8iX5mnODprNz5y9LY6dAsPDpGGX2kBYgOI4nW0RYF3DNYOQ1gGCFQRGc7THrH5yFtVhRbgtA7GZkVMEJEduDtbltU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: KUYPR06MB8531 Received-SPF: pass client-ip=2a01:111:f403:c40f::6; envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The DMA flash address register (SPI084) holds the offset of the=0A= flash access within the controller's flash window. The AST2700 FMC,=0A= SPI0 and SPI1 controllers use a dma_flash_mask of 0x2FFFFFFC, which=0A= clears bit 28, and SPI2 uses 0x0FFFFFFC, which limits DMA to the=0A= first 256MB of the window.=0A= =0A= With the default segment layout, FMC CS2 is mapped at offset=0A= 0x10000000. A DMA read from that offset is masked to 0x0 and returns=0A= data from CS0 instead of CS2.=0A= =0A= The Linux driver programs SPI084 with the window offset masked by=0A= 0x7fffffff, so bit 28 is a valid address bit.=0A= =0A= Set dma_flash_mask to 0x3FFFFFFC for all AST2700 controllers to cover=0A= the full 1GB flash window.=0A= =0A= Fixes: bdb3748dba30 ("aspeed/smc: Add AST2700 support")=0A= Signed-off-by: Jamin Lin =0A= Reviewed-by: Philippe Mathieu-Daud=E9 =0A= ---=0A= hw/ssi/aspeed_smc.c | 8 ++++----=0A= 1 file changed, 4 insertions(+), 4 deletions(-)=0A= =0A= diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c=0A= index 10ea9e5aa0..c0c3666dbc 100644=0A= --- a/hw/ssi/aspeed_smc.c=0A= +++ b/hw/ssi/aspeed_smc.c=0A= @@ -1952,7 +1952,7 @@ static void aspeed_2700_fmc_class_init(ObjectClass *k= lass, const void *data)=0A= asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |=0A= ASPEED_SMC_FEATURE_DATA_FIFO;=0A= - asc->dma_flash_mask =3D 0x2FFFFFFC;=0A= + asc->dma_flash_mask =3D 0x3FFFFFFC;=0A= asc->dma_dram_mask =3D 0xFFFFFFFC;=0A= asc->dma_start_length =3D 1;=0A= asc->nregs =3D (0x200 + (asc->cs_num_max * 0x10)) >> 2;=0A= @@ -1989,7 +1989,7 @@ static void aspeed_2700_spi0_class_init(ObjectClass *= klass, const void *data)=0A= asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |=0A= ASPEED_SMC_FEATURE_DATA_FIFO;=0A= - asc->dma_flash_mask =3D 0x2FFFFFFC;=0A= + asc->dma_flash_mask =3D 0x3FFFFFFC;=0A= asc->dma_dram_mask =3D 0xFFFFFFFC;=0A= asc->dma_start_length =3D 1;=0A= asc->nregs =3D (0x200 + (asc->cs_num_max * 0x10)) >> 2;=0A= @@ -2025,7 +2025,7 @@ static void aspeed_2700_spi1_class_init(ObjectClass *= klass, const void *data)=0A= asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |=0A= ASPEED_SMC_FEATURE_DATA_FIFO;=0A= - asc->dma_flash_mask =3D 0x2FFFFFFC;=0A= + asc->dma_flash_mask =3D 0x3FFFFFFC;=0A= asc->dma_dram_mask =3D 0xFFFFFFFC;=0A= asc->dma_start_length =3D 1;=0A= asc->nregs =3D (0x200 + (asc->cs_num_max * 0x10)) >> 2;=0A= @@ -2061,7 +2061,7 @@ static void aspeed_2700_spi2_class_init(ObjectClass *= klass, const void *data)=0A= asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |=0A= ASPEED_SMC_FEATURE_DATA_FIFO;=0A= - asc->dma_flash_mask =3D 0x0FFFFFFC;=0A= + asc->dma_flash_mask =3D 0x3FFFFFFC;=0A= asc->dma_dram_mask =3D 0xFFFFFFFC;=0A= asc->dma_start_length =3D 1;=0A= asc->nregs =3D (0x200 + (asc->cs_num_max * 0x10)) >> 2;=0A= -- =0A= 2.53.0=0A=