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Wed, 28 Oct 2026 02:32:00 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Kane Chen , Alistair Francis , Kevin Wolf , Hanna Reitz , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: Jamin Lin , Troy Lee Subject: [PATCH v2 05/13] hw/ssi/aspeed_smc: Add AST1040 FMC and SPI controllers Thread-Topic: [PATCH v2 05/13] hw/ssi/aspeed_smc: Add AST1040 FMC and SPI controllers Thread-Index: AQHdZoSCkchUXX8rRUag14Z5z69XiA== Date: Wed, 28 Oct 2026 02:31:59 +0000 Message-ID: <20261028023154.48395-6-jamin_lin@aspeedtech.com> References: <20261028023154.48395-1-jamin_lin@aspeedtech.com> In-Reply-To: <20261028023154.48395-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SEZPR06MB7362:EE_|KUYPR06MB8531:EE_ x-ms-office365-filtering-correlation-id: 5d0d15c4-5514-4e57-6b88-08df349ba4d9 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Archived-By: MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SEZPR06MB7362.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5d0d15c4-5514-4e57-6b88-08df349ba4d9 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Oct 2026 02:31:59.9575 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: lVjd1RgmBd+chTCHaMdY4CXgPXN6stTdJxvRBww4diBzZveXQ1I2cNVNCpR7Vza/wJPdXfpcuxvZTF1cCpNUYXdCb9o6LQFbZMiyRibjYXc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: KUYPR06MB8531 Received-SPF: pass client-ip=2a01:111:f403:c40f::6; envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The AST1040 FMC and SPI controllers are compatible with the AST2700=0A= controllers, but use different flash window. Therefore, the AST2700=0A= controller types cannot be reused directly for AST1040.=0A= =0A= Add dedicated AST1040 FMC, SPI0 and SPI1 controller types with the=0A= appropriate parameter settings.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/ssi/aspeed_smc.c | 119 ++++++++++++++++++++++++++++++++++++++++++++=0A= 1 file changed, 119 insertions(+)=0A= =0A= diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c=0A= index c0c3666dbc..ec9ad0f747 100644=0A= --- a/hw/ssi/aspeed_smc.c=0A= +++ b/hw/ssi/aspeed_smc.c=0A= @@ -2072,6 +2072,110 @@ static void aspeed_2700_spi2_class_init(ObjectClass= *klass, const void *data)=0A= asc->reg_ops =3D &aspeed_2700_smc_flash_ops;=0A= }=0A= =0A= +static const uint32_t aspeed_1040_resets[ASPEED_SMC_R_MAX] =3D {=0A= + [R_CONF] =3D (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |=0A= + CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1 |=0A= + CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2 |=0A= + CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE3),=0A= +};=0A= +=0A= +static void aspeed_1040_fmc_class_init(ObjectClass *klass, const void *dat= a)=0A= +{=0A= + DeviceClass *dc =3D DEVICE_CLASS(klass);=0A= + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass);=0A= +=0A= + dc->desc =3D "Aspeed 1040 FMC Controller";=0A= + asc->r_conf =3D R_CONF;=0A= + asc->r_ce_ctrl =3D R_CE_CTRL;=0A= + asc->r_ctrl0 =3D R_CTRL0;=0A= + asc->r_timings =3D R_TIMINGS;=0A= + asc->nregs_timings =3D 2;=0A= + asc->conf_enable_w0 =3D CONF_ENABLE_W0;=0A= + asc->cs_num_max =3D 2;=0A= + asc->segments =3D aspeed_2700_spi0_segments;=0A= + asc->segment_addr_mask =3D 0xffffffff;=0A= + asc->resets =3D aspeed_1040_resets;=0A= + asc->flash_window_base =3D 0x80000000;=0A= + asc->flash_window_size =3D 512 * MiB;=0A= + asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;=0A= + asc->dma_flash_mask =3D 0x1FFFFFFC;=0A= + asc->dma_dram_mask =3D 0x00FFFFFC;=0A= + asc->dma_start_length =3D 1;=0A= + asc->nregs =3D ASPEED_SMC_R_MAX;=0A= + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg;=0A= + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment;=0A= + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl;=0A= + asc->reg_ops =3D &aspeed_2700_smc_flash_ops;=0A= +}=0A= +=0A= +static const AspeedSegments aspeed_1040_spi0_segments[] =3D {=0A= + { 0x0, 128 * MiB },=0A= + { 128 * MiB, 128 * MiB },=0A= + { 256 * MiB, 128 * MiB },=0A= + { 384 * MiB, 128 * MiB },=0A= +};=0A= +=0A= +static void aspeed_1040_spi0_class_init(ObjectClass *klass, const void *da= ta)=0A= +{=0A= + DeviceClass *dc =3D DEVICE_CLASS(klass);=0A= + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass);=0A= +=0A= + dc->desc =3D "Aspeed 1040 SPI0 Controller";=0A= + asc->r_conf =3D R_CONF;=0A= + asc->r_ce_ctrl =3D R_CE_CTRL;=0A= + asc->r_ctrl0 =3D R_CTRL0;=0A= + asc->r_timings =3D R_TIMINGS;=0A= + asc->nregs_timings =3D 4;=0A= + asc->conf_enable_w0 =3D CONF_ENABLE_W0;=0A= + asc->cs_num_max =3D 4;=0A= + asc->segments =3D aspeed_1040_spi0_segments;=0A= + asc->segment_addr_mask =3D 0xffffffff;=0A= + asc->resets =3D aspeed_1040_resets;=0A= + asc->flash_window_base =3D 0xA0000000;=0A= + asc->flash_window_size =3D 512 * MiB;=0A= + asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;=0A= + asc->dma_flash_mask =3D 0x1FFFFFFC;=0A= + asc->dma_dram_mask =3D 0x00FFFFFC;=0A= + asc->dma_start_length =3D 1;=0A= + asc->nregs =3D ASPEED_SMC_R_MAX;=0A= + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg;=0A= + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment;=0A= + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl;=0A= + asc->reg_ops =3D &aspeed_2700_smc_flash_ops;=0A= +}=0A= +=0A= +static void aspeed_1040_spi1_class_init(ObjectClass *klass, const void *da= ta)=0A= +{=0A= + DeviceClass *dc =3D DEVICE_CLASS(klass);=0A= + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass);=0A= +=0A= + dc->desc =3D "Aspeed 1040 SPI1 Controller";=0A= + asc->r_conf =3D R_CONF;=0A= + asc->r_ce_ctrl =3D R_CE_CTRL;=0A= + asc->r_ctrl0 =3D R_CTRL0;=0A= + asc->r_timings =3D R_TIMINGS;=0A= + asc->nregs_timings =3D 2;=0A= + asc->conf_enable_w0 =3D CONF_ENABLE_W0;=0A= + asc->cs_num_max =3D 2;=0A= + asc->segments =3D aspeed_2700_spi0_segments;=0A= + asc->segment_addr_mask =3D 0xffffffff;=0A= + asc->resets =3D aspeed_1040_resets;=0A= + asc->flash_window_base =3D 0xC0000000;=0A= + asc->flash_window_size =3D 512 * MiB;=0A= + asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;=0A= + asc->dma_flash_mask =3D 0x1FFFFFFC;=0A= + asc->dma_dram_mask =3D 0x00FFFFFC;=0A= + asc->dma_start_length =3D 1;=0A= + asc->nregs =3D ASPEED_SMC_R_MAX;=0A= + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg;=0A= + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment;=0A= + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl;=0A= + asc->reg_ops =3D &aspeed_2700_smc_flash_ops;=0A= +}=0A= +=0A= static const TypeInfo aspeed_smc_types[] =3D {=0A= {=0A= .name =3D TYPE_ASPEED_SMC_FLASH,=0A= @@ -2103,6 +2207,21 @@ static const TypeInfo aspeed_smc_types[] =3D {=0A= .parent =3D TYPE_ASPEED_SMC,=0A= .class_init =3D aspeed_1030_spi2_class_init,=0A= },=0A= + {=0A= + .name =3D "aspeed.fmc-ast1040",=0A= + .parent =3D TYPE_ASPEED_SMC,=0A= + .class_init =3D aspeed_1040_fmc_class_init,=0A= + },=0A= + {=0A= + .name =3D "aspeed.spi0-ast1040",=0A= + .parent =3D TYPE_ASPEED_SMC,=0A= + .class_init =3D aspeed_1040_spi0_class_init,=0A= + },=0A= + {=0A= + .name =3D "aspeed.spi1-ast1040",=0A= + .parent =3D TYPE_ASPEED_SMC,=0A= + .class_init =3D aspeed_1040_spi1_class_init,=0A= + },=0A= {=0A= .name =3D "aspeed.smc-ast2400",=0A= .parent =3D TYPE_ASPEED_SMC,=0A= -- =0A= 2.53.0=0A=