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envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, KHOP_DYNAMIC=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-21.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Nikhil Kumar Singh A guest-triggerable assertion crash (DoS) exists in pnv_phb4_config_write() and pnv_phb4_config_read(). When a guest performs an 8-byte access to PHB_CONFIG_DATA (offset 0x130), QEMU aborts because the switch(size) statement in the config accessors only handles 1, 2, and 4-byte accesses, hitting g_assert_not_reached() in the default case. Since guest input is untrusted, an invalid access size should not crash the host. Fix this by adding a size > 4 guard in pnv_phb4_reg_write() and pnv_phb4_reg_read() before the config accessor calls, and by replacing the g_assert_not_reached() in pnv_phb4_config_write() and pnv_phb4_config_read() with phb_error() to cover any other callers. Invalid reads now return ~0ull, maintaining PCI conventions. Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3591 Signed-off-by: Nikhil Kumar Singh Reviewed-by: Aditya Gupta Link: https://lore.kernel.org/qemu-devel/20260805090530.1333997-1-nikhilks@linux.ibm.com Signed-off-by: Harsh Prateek Bora --- hw/pci-host/pnv_phb4.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 9acaf4c0c2..ac09a0b034 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -84,7 +84,9 @@ static void pnv_phb4_config_write(PnvPHB4 *phb, unsigned off, val = bswap32(val); break; default: - g_assert_not_reached(); + phb_error(phb, "invalid config write size %u at offset 0x%x\n", + size, off); + return; } pci_host_config_write_common(pdev, cfg_addr, limit, val, size); } @@ -119,7 +121,9 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off, case 4: return bswap32(val); default: - g_assert_not_reached(); + phb_error(phb, "invalid config read size %u at offset 0x%x\n", + size, off); + return ~0ull; } } @@ -507,6 +511,11 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, /* Special case outbound configuration data */ if ((off & 0xfffc) == PHB_CONFIG_DATA) { + if (size > 4) { + phb_error(phb, "invalid config write size %u at 0x%"PRIx64"\n", + size, off); + return; + } pnv_phb4_config_write(phb, off & 0x3, size, val); return; } @@ -644,6 +653,11 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) uint64_t val; if ((off & 0xfffc) == PHB_CONFIG_DATA) { + if (size > 4) { + phb_error(phb, "invalid config read size %u at 0x%"PRIx64"\n", + size, off); + return ~0ull; + } return pnv_phb4_config_read(phb, off & 0x3, size); } -- 2.52.0