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Tsirkin" To: =?iso-8859-1?Q?Cl=E9ment?= MATHIEU--DRIF Cc: "qemu-devel@nongnu.org" , "odaki@rsg.ci.i.u-tokyo.ac.jp" Subject: Re: [PATCH] pcie_sriov: Avoid capability structure overflow in PF reset Message-ID: <20261028095024-mutt-send-email-mst@kernel.org> References: <20260921055917.715685-1-clement.mathieu--drif@bull.com> <20261028091349-mutt-send-email-mst@kernel.org> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Wed, Oct 28, 2026 at 01:40:24PM +0000, Clément MATHIEU--DRIF wrote: > > On Wed, 2026-10-28 at 09:14 -0400, Michael S. Tsirkin wrote: > > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. > > > > > > On Mon, Sep 21, 2026 at 05:59:23AM +0000, Clément MATHIEU--DRIF wrote: > > > > > The SR-IOV PCIe capability exposes 6 regions (no ROM), each with a > > > dedicated 32-bit configuration field. Fix the reset loop to write > > > 32 bits instead of 64 bits and stop after PCI_SRIOV_NUM_BARS iterations. > > > > > > As a side effect of this change, update PCIESriovPF::vf_bar_type > > > to match the number of regions exposed by SR-IOV and rework the > > > associated assert statements. > > > > > > Fixes: c8bc4db403e1 ("pcie_sriov: Reset SR-IOV extended capability") > > > Signed-off-by: Clement Mathieu--Drif <[clement.mathieu--drif@bull.com](mailto:clement.mathieu--drif@bull.com)> > > > > > > I queued another patch fixing this, yours will become a cleanup. > > Once my pull is merged, pls rebase and report. > > > > Thanks! > > Hi Michael, > > Do you want version rebased on master or another ref? > > cmd pci branch in my tree will do > > > > > > > --- > > >  hw/pci/pcie_sriov.c         | 9 +++++---- > > >  include/hw/pci/pcie_sriov.h | 2 +- > > >  2 files changed, 6 insertions(+), 5 deletions(-) > > > > > > diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c > > > index c41ac95bee..df61f281ea 100644 > > > --- a/hw/pci/pcie_sriov.c > > > +++ b/hw/pci/pcie_sriov.c > > > @@ -229,8 +229,7 @@ void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, > > > > > >      assert(sriov_cap > 0); > > >      assert(region_num >= 0); > > > -    assert(region_num < PCI_NUM_REGIONS); > > > -    assert(region_num != PCI_ROM_SLOT); > > > +    assert(region_num < PCI_SRIOV_NUM_BARS); > > > > > >      wmask = ~(size - 1); > > >      addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4; > > > @@ -344,6 +343,8 @@ int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDevice *dev, > > >      dev->exp.sriov_pf.vf = vfs; > > >      dev->exp.sriov_pf.vf_user_created = true; > > > > > > +    assert(vfs[0]->io_regions[PCI_ROM_SLOT].size == 0); > > > + > > >      for (i = 0; i < PCI_NUM_REGIONS; i++) { > > >          PCIIORegion *region = &vfs[0]->io_regions[i]; > > > > > > @@ -463,8 +464,8 @@ void pcie_sriov_pf_reset(PCIDevice *dev) > > >       */ > > >      pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); > > > > > > -    for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { > > > -        pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, > > > +    for (uint16_t i = 0; i < PCI_SRIOV_NUM_BARS; i++) { > > > +        pci_set_long(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, > > >                       dev->exp.sriov_pf.vf_bar_type[i]); > > >      } > > >  } > > > diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h > > > index b0ea6a62c7..5f81e3b1bb 100644 > > > --- a/include/hw/pci/pcie_sriov.h > > > +++ b/include/hw/pci/pcie_sriov.h > > > @@ -16,7 +16,7 @@ > > >  #include "hw/pci/pci.h" > > > > > >  typedef struct PCIESriovPF { > > > -    uint8_t vf_bar_type[PCI_NUM_REGIONS];   /* Store type for each VF bar */ > > > +    uint8_t vf_bar_type[PCI_SRIOV_NUM_BARS];   /* Store type for each VF bar */ > > >      PCIDevice **vf;     /* Pointer to an array of num_vfs VF devices */ > > >      bool vf_user_created; /* If VFs are created by user */ > > >  } PCIESriovPF; > > > -- > > > 2.55.0 > > > >