From: Fuad Tabba <fuad.tabba@linux.dev>
To: Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@kernel.org>,
kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Steffen Eiden <seiden@linux.ibm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Vincent Donnefort <vdonnefort@google.com>,
kernel-team@android.com, linux-kernel@vger.kernel.org,
Oculytic <oculytic@gmail.com>, Fuad Tabba <tabba@google.com>
Subject: [PATCH v3 3/3] KVM: arm64: Disable host PMU counters for protected guests
Date: Wed, 28 Oct 2026 15:31:52 +0000 [thread overview]
Message-ID: <20261028153152.1740044-4-fuad.tabba@linux.dev> (raw)
In-Reply-To: <20261028153152.1740044-1-fuad.tabba@linux.dev>
A protected guest has no PMU, and EL2 clears MDCR_EL2.HPME for it.
However, __pkvm_vcpu_load() sets HPMN to cover every event counter, so
HPME has no effect and the counters the host has enabled keep counting
the guest.
Clear PMCR_EL0.E in the world switch while a protected guest runs, which
stops them all. Gate this on system_supports_pmuv3(), as
__activate_traps_common() does for PMUSERENR_EL0.
Side channels are outside pKVM's threat model, so this is hardening
rather than a fix.
Reported-by: Oculytic <oculytic@gmail.com>
Signed-off-by: Fuad Tabba <fuad.tabba@linux.dev>
---
arch/arm64/kvm/hyp/nvhe/switch.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c
index 91e1edf40bcd2..003469e85ed46 100644
--- a/arch/arm64/kvm/hyp/nvhe/switch.c
+++ b/arch/arm64/kvm/hyp/nvhe/switch.c
@@ -175,6 +175,26 @@ static void __pmu_switch_to_host(struct kvm_vcpu *vcpu)
#define __pmu_switch_to_host(v) do {} while (0)
#endif
+static u64 __pmu_stop_host_counters(struct kvm_vcpu *vcpu)
+{
+ u64 pmcr;
+
+ if (!vcpu_is_protected(vcpu) || !system_supports_pmuv3())
+ return 0;
+
+ pmcr = read_sysreg(pmcr_el0);
+ if (pmcr & ARMV8_PMU_PMCR_E)
+ write_sysreg(pmcr & ~ARMV8_PMU_PMCR_E, pmcr_el0);
+
+ return pmcr;
+}
+
+static void __pmu_restore_host_counters(u64 pmcr)
+{
+ if (pmcr & ARMV8_PMU_PMCR_E)
+ write_sysreg(pmcr, pmcr_el0);
+}
+
/*
* Handler for protected VM MSR, MRS or System instruction execution in AArch64.
*
@@ -283,6 +303,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
struct kvm_s2_mmu *mmu;
bool pmu_switch_needed;
u64 exit_code;
+ u64 host_pmcr;
/*
* Having IRQs masked via PMR when entering the guest means the GIC
@@ -300,6 +321,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
guest_ctxt = &vcpu->arch.ctxt;
pmu_switch_needed = __pmu_switch_to_guest(vcpu);
+ host_pmcr = __pmu_stop_host_counters(vcpu);
__sysreg_save_state_nvhe(host_ctxt);
/*
@@ -384,6 +406,8 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
if (pmu_switch_needed)
__pmu_switch_to_host(vcpu);
+ __pmu_restore_host_counters(host_pmcr);
+
/* Returning to host will clear PSR.I, remask PMR if needed */
if (system_uses_irq_prio_masking())
gic_write_pmr(GIC_PRIO_IRQOFF);
--
2.47.3
prev parent reply other threads:[~2026-10-28 15:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-28 15:31 [PATCH v3 0/3] KVM: arm64: Fix PMU handling in pKVM Fuad Tabba
2026-10-28 15:31 ` [PATCH v3 1/3] KVM: arm64: Synchronise kvm_host_data before host deprivileging Fuad Tabba
2026-10-28 15:31 ` [PATCH v3 2/3] KVM: arm64: Pass the PMU events to the hyp vCPU of non-protected guests Fuad Tabba
2026-10-28 15:31 ` Fuad Tabba [this message]
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