From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793213685; b=kZ+xC2GGPgAmAQdlQwNY0iRR9XNkSiTUlHdrlLP/pYiswmJBvYcg/QS2b80iSlil5YOT tW7vBxGfHFXhtYpGYFmMSuvYbVjSITzRMBEexQuYEMzfEkiJ/1Ls5xqfHY+/LVNAnhmh/ sS4g2KwTaRNPm13FghRPLozlgCv2WY1kBowdTtsHN3qIG1nwgzzhWs53l49zABHHhF2Zt 0qP5ih8sNEBWL/Twi5JvhY+c5W3xIVNyuoeWU8HnPoS3Ae6cB7bkl21Cc+i8VSKs7eaDJ iyTPP5ultrOn7L34TsG8OaIGc4vvHkLbvq9X9rN4xo1Pg4V/FQXy8edIYwMj6fhTCZg== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793213685; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:User-Agent:X-stable:X-Patchwork-Hint: MIME-Version:Content-Transfer-Encoding; bh=iHRyYCnmSUk/e8U2d7J2zlTq52//2t9mlgb0q+bvd4o=; b=aKfe9uwqOehDL4xt9Onph8EBeT+Sb4C2JJBDO0Jo759hsz0rKsUfTLSJFvNlVU7bwthb 0TR7MJgnzJ9Vu2X8Ffd8pGILpEpA/fh3EXw05gVI+rX1tYupp6JdFbZbW06VFh8NxmsN7 XtV1EST0VnpqvKUbNdeKyo+Pw/lWGInagkULS1swQ9Eh64YVtkMeQ+FR3jBfLI4qcp+EO zrMkMs9XhWa+noA1iOBsidefNareMji3wYW72gDDcD//GaHldIY1uwb865H4/DMT/bAzx gXdF9yofg2xcqR8fa0IJCjrP4FpFb/Wmk44UgbdfNYwZykS/Gngrjz6IeRo3O/63Tww== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=NjcAVkMf; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 675AE606A33D; Wed, 28 Oct 2026 18:54:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key, unprotected) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=NjcAVkMf Received: by smtp.kernel.org (Postfix) with ESMTPSA id 770621F01825; Wed, 28 Oct 2026 18:54:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1793213685; bh=iHRyYCnmSUk/e8U2d7J2zlTq52//2t9mlgb0q+bvd4o=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=NjcAVkMfLm0zTeaM2lDu42q736gkZzZIg3QzW4KJXqTvwhX0/oKAncnKNUxCrAvYl LdovfqFyaUl5aZKNwc3jLHu37RR4Wva197tvhcGrU5/vDVi7V2R7bAqQmeUYGjZNQZ 33nHTHZt+1Rb73j5eQd6vQ/JxSLhAj9/osjQERmM= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Anup Patel , Andrew Jones , Atish Patra , Sasha Levin Subject: [PATCH 6.1 0594/1887] perf: RISC-V: Define helper functions expose hpm counter width and count Date: Wed, 28 Oct 2026 17:44:50 +0100 Message-ID: <20261028170512.935769327@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261028170459.200466217@linuxfoundation.org> References: <20261028170459.200466217@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore X-Mailing-List: patches@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Atish Patra [ Upstream commit 585e351ff359c032ea7ab48d999b252ba09f8051 ] KVM module needs to know how many hardware counters and the counter width that the platform supports. Otherwise, it will not be able to show optimal value of virtual counters to the guest. The virtual hardware counters also need to have the same width as the logical hardware counters for simplicity. However, there shouldn't be mapping between virtual hardware counters and logical hardware counters. As we don't support hetergeneous harts or counters with different width as of now, the implementation relies on the counter width of the first available programmable counter. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra Signed-off-by: Anup Patel Stable-dep-of: 34b567868777 ("perf: RISCV: Fix panic on pmu overflow handler") Signed-off-by: Sasha Levin --- drivers/perf/riscv_pmu_sbi.c | 37 ++++++++++++++++++++++++++++++++-- include/linux/perf/riscv_pmu.h | 3 +++ 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 5aab43a3ffb92..622fe7c982509 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -43,12 +43,15 @@ static const struct attribute_group *riscv_pmu_attr_groups[] = { }; /* - * RISC-V doesn't have hetergenous harts yet. This need to be part of + * RISC-V doesn't have heterogeneous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ static union sbi_pmu_ctr_info *pmu_ctr_list; static unsigned int riscv_pmu_irq; +/* Cache the available counters in a bitmask */ +static unsigned long cmask; + struct sbi_pmu_event_data { union { union { @@ -264,6 +267,37 @@ static bool pmu_sbi_ctr_is_fw(int cidx) return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false; } +/* + * Returns the counter width of a programmable counter and number of hardware + * counters. As we don't support heterogeneous CPUs yet, it is okay to just + * return the counter width of the first programmable counter. + */ +int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr) +{ + int i; + union sbi_pmu_ctr_info *info; + u32 hpm_width = 0, hpm_count = 0; + + if (!cmask) + return -EINVAL; + + for_each_set_bit(i, &cmask, RISCV_MAX_COUNTERS) { + info = &pmu_ctr_list[i]; + if (!info) + continue; + if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET) + hpm_width = info->width; + if (info->type == SBI_PMU_CTR_TYPE_HW) + hpm_count++; + } + + *hw_ctr_width = hpm_width; + *num_hw_ctr = hpm_count; + + return 0; +} +EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info); + static int pmu_sbi_ctr_get_idx(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; @@ -798,7 +832,6 @@ static void riscv_pmu_destroy(struct riscv_pmu *pmu) static int pmu_sbi_device_probe(struct platform_device *pdev) { struct riscv_pmu *pmu = NULL; - unsigned long cmask = 0; int ret = -ENODEV; int num_counters; diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index e17e86ad6f3a2..a1c3f77714810 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -73,6 +73,9 @@ void riscv_pmu_legacy_skip_init(void); static inline void riscv_pmu_legacy_skip_init(void) {}; #endif struct riscv_pmu *riscv_pmu_alloc(void); +#ifdef CONFIG_RISCV_PMU_SBI +int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); +#endif #endif /* CONFIG_RISCV_PMU */ -- 2.53.0