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Thu, 29 Oct 2026 02:04:07 -0500 Received: from JesseDEV.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.53 via Frontend Transport; Thu, 29 Oct 2026 02:04:06 -0500 From: Jesse Zhang To: CC: , Christian Koenig , Prike Liang , Sunil Khatri , Jesse Zhang Subject: [PATCH 2/3] drm/amdgpu/gfx12: disallow GFXOFF while updating the SPM VMID Date: Thu, 29 Oct 2026 15:03:25 +0800 Message-ID: <20261029070403.22012-2-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20261029070403.22012-1-Jesse.Zhang@amd.com> References: <20261029070403.22012-1-Jesse.Zhang@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022571:EE_|DM4PR12MB6157:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ea92b8e-3097-4b5e-e69a-08df358ad38c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022571.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6157 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 gfx_v12_0_update_spm_vmid() does a read-modify-write of RLC_SPM_MC_CNTL over MMIO without keeping GFX powered, unlike gfx11. When GFX is in GFXOFF at that point the update doesn't stick, and with the SPM VMID programmed on submission again, the job of a process with a reserved VMID can still run with the SPM writing through VMID 0. On navi48, after a few other submissions and a VM fault on the same VM, a COPY_DATA of RLC_SPM_MC_CNTL from such a job reads 0 although the update was called for it: $ run testcase: cs-secure-ib-compute,gem-mapping-info-high-va,reserved-vmid-spm-vmid amdgpu 0000:03:00.0: [gfxhub] page fault (src_id:0 ring:40 vmid:7 pasid:185) amdgpu 0000:03:00.0: Faulty UTCL2 client ID: SDMA1 (0xe) RLC_SPM_MC_CNTL in the job: 0x00000000 With GFXOFF disallowed around the update it reads the reserved VMID 15. Fixes: 52cb80c12e8a ("drm/amdgpu: Add gfx v12_0 ip block support (v6)") Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index d334fb805020..9bdd82cc202d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3963,6 +3963,7 @@ static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, { u32 reg, data; + amdgpu_gfx_off_ctrl(adev, false); reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); if (amdgpu_sriov_is_pp_one_vf(adev)) data = RREG32_NO_KIQ(reg); @@ -3976,6 +3977,7 @@ static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); else WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); + amdgpu_gfx_off_ctrl(adev, true); } static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { -- 2.50.1