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This will allow to easily diff with the future content, automatically generated. No functional change intended. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Shameer Kolothum Reviewed-by: Khushit Shah --- v5 -> v6: - v5 version conflicted because ID_AA64FPFR0_EL1 has been added v4 -> v5: - remove spurious CCSIDR definition --- target/arm/cpu-sysregs.h.inc | 46 ++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index d9e058a57e..b5c7970971 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) -DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) -DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) -DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) -DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) -DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) -DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF_MUX(CCSIDR_EL1, 3, 1, 0, 0, 0, 16) +DEF(CLIDR_EL1, 3, 1, 0, 0, 1) +DEF(CTR_EL0, 3, 3, 0, 0, 1) +DEF(DCZID_EL0, 3, 3, 0, 0, 7) DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) +DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) +DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) @@ -17,30 +17,30 @@ DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) -DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) -DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) -DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) +DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) +DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) +DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3) -DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) -DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) -DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) -DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7) +DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) DEF(ID_ISAR0_EL1, 3, 0, 0, 2, 0) DEF(ID_ISAR1_EL1, 3, 0, 0, 2, 1) DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2) DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3) DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4) DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5) -DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7) +DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) +DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) +DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) +DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7) +DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) +DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) +DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) +DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) +DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) -DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) -DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) -DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) -DEF_MUX(CCSIDR_EL1, 3, 1, 0, 0, 0, 16) -DEF(CLIDR_EL1, 3, 1, 0, 0, 1) -DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) -DEF(CTR_EL0, 3, 3, 0, 0, 1) -DEF(DCZID_EL0, 3, 3, 0, 0, 7) -- 2.53.0