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[189.203.100.56]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4a904856efesm10668fac.6.2026.10.29.10.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 10:14:38 -0700 (PDT) Date: Thu, 29 Oct 2026 11:14:35 -0600 From: Tom Rini To: Abhilash V Cc: ilias.apalodimas@linaro.org, aswin.murugan@oss.qualcomm.com, casey.connolly@linaro.org, neil.armstrong@linaro.org, sumit.garg@kernel.org, lukma@nabladev.com, peng.fan@nxp.com, jh80.chung@samsung.com, tanmay.kathpalia@altera.com, sjg@chromium.org, Michael.Srba@seznam.cz, varadarajan.narayanan@oss.qualcomm.com, nikroks@mainlining.org, balaji.selvanathan@oss.qualcomm.com, nathbappai@gmail.com, jbx6244@gmail.com, u-boot@lists.u-boot-project.org, u-boot-qcom@groups.io Subject: Re: [PATCH v5 09/13] arm: qcom: enable MMU and cache setup for Shikra SPL Message-ID: <20261029171435.GA3011578@bill-the-cat> References: <20261029105746.3487456-1-abhilash.v@oss.qualcomm.com> <20261029105746.3487456-10-abhilash.v@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="k0kTrwpUIJx/tq+4" Content-Disposition: inline In-Reply-To: <20261029105746.3487456-10-abhilash.v@oss.qualcomm.com> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 --k0kTrwpUIJx/tq+4 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Oct 29, 2026 at 03:57:42AM -0700, Abhilash V wrote: > Use Shikra fixed pre-DDR memory map when enabling caches in > SPL. Allocate page tables from the early malloc-F heap and > select the board map through a common Qualcomm hook. >=20 > Signed-off-by: Abhilash V [snip] > +/* > + * SPL platforms whose pre-DRAM address map differs from the common Qual= comm > + * map may override this hook. > + */ > +struct mm_region *__weak qcom_spl_mem_map(void) > +{ > + return NULL; > +} [snip] > @@ -192,7 +208,11 @@ void enable_caches(void) > =20 > gd->arch.tlb_fillptr =3D tlb_addr; > =20 > - build_mem_map(); > + spl_mem_map =3D qcom_spl_mem_map(); > + if (spl_mem_map) > + mem_map =3D spl_mem_map; > + else > + build_mem_map(); This is kind of odd. Which pre-requisite series brings this in? I wonder if a better abstraction would help, and if this is still the right way to go, the weak part should come in then. --=20 Tom --k0kTrwpUIJx/tq+4 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTzzqh0PWDgGS+bTHor4qD1Cr/kCgUCauN+9wAKCRAr4qD1Cr/k CsRJAQCvMPZBV1crexe9NK9r75S8fLuZ+58gwfZ4t1HUjoTn+gD9FmbIINyNcqOH O07b+Ev1mG+e9BU33D+hSn6/QJXjggI= =fO/2 -----END PGP SIGNATURE----- --k0kTrwpUIJx/tq+4--