[PATCH 2/3] arm64: dts: agilex5: define the i2c0 pins for pinctrl

[Dinh Nguyen <dinguyen@kernel.org>]

Add the I2C pins definition to the Agilex5 SoCDK NAND daughter card. This
allows the I2C driver to use pinctrl on the pins to perform I2C recovery.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 .../dts/altera/socfpga_agilex5_socdk_nand.dts | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_agilex5_socdk_nand.dts
index 81443096cf991..346a4ee22f95b 100644
--- a/arch/arm64/boot/dts/altera/socfpga_agilex5_socdk_nand.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_agilex5_socdk_nand.dts
@@ -39,6 +39,22 @@ memory@80000000 {
 	};
 };
 
+&pinctrl0 {
+	i2c0_pmx_func: i2c0-pmx-func-pins {
+		pinctrl-single,pins = <
+			0x10   0x4   /* I2C0_SDA (IOA4) PIN4SEL) */
+			0x14   0x4   /* I2C0_SCL (IOA5) PIN5SEL */
+		>;
+	};
+
+	i2c0_pmx_func_gpio: i2c0-pmx-func-gpio-pins {
+		pinctrl-single,pins = <
+			0x10   0x8   /* I2C0_SDA (IOA4) PIN4SEL) */
+			0x14   0x8   /* I2C0_SCL (IOA5) PIN5SEL */
+		>;
+	};
+};
+
 &gmac0 {
 	status = "okay";
 	phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
@@ -66,6 +82,10 @@ &gpio1 {
 
 &i2c0 {
 	status = "okay";
+
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&i2c0_pmx_func>;
+	pinctrl-1 = <&i2c0_pmx_func_gpio>;
 };
 
 &i3c0 {
-- 
2.42.0.411.g813d9a9188