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client-ip=5.75.144.95; helo=mail.mainlining.org; envelope-from=brads@mainlining.org; receiver= Authentication-Results: smtp2.osuosl.org; dmarc=pass (p=reject dis=none) header.from=mainlining.org Authentication-Results: smtp2.osuosl.org; dkim=pass (2048-bit key, unprotected) header.d=mainlining.org header.i=@mainlining.org header.a=rsa-sha256 header.s=202507r header.b=qLFPZwUi; dkim=pass header.d=mainlining.org header.i=@mainlining.org header.a=ed25519-sha256 header.s=202507e header.b=jbEb/6gi Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) by smtp2.osuosl.org (Postfix) with UTF8SMTPS id 317B14051A for ; Fri, 30 Oct 2026 01:49:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; s=202507r; d=mainlining.org; c=relaxed/relaxed; h=Message-ID:Date:Subject:To:From; t=1793324964; bh=PDFHKyubS0i+1JBa/3ASvBt bVqkak3OLRYLOP72VDVQ=; b=qLFPZwUi+VcgKuCaLhJAwUJUjLqx2KTOxTio9teeVGnoyzKpk9 zprw5xML5NhzzV02okTaDdz+NMDsobQwnj8Jx3ToUigQE9Y+WcYxqE1A8eT8u+bEOTCjrAbCleL CpjH5hE3NWDPDZ+IrVnprVInNypD2OquhrwyybuG0JYYqm7BayFIrl0oGQyx1yN+oRKkmF9itP6 cy8kIM/1uQdLn4x2eozciWDAu3QiWtARiFlafvuNZR6m/t9Fr5TIWh6a0apcoTAPe9lXQPYtDuZ BvbjA+YBf9mUP9P1LONeyhgsGaipV9OwCZFEMpwbeCmytyaAAEPnDMQtiMnnX6cUs8w==; DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=Message-ID:Date:Subject:To:From; t=1793324964; bh=PDFHKyubS0i+1JBa/3ASvBt bVqkak3OLRYLOP72VDVQ=; b=jbEb/6giak9bcZ+JcXECVI3UkAMt+2LBL4pC2uBUDt0XNn5y0I lu1tIGxnUmVXwliRwRR9FxRFgQx5wkzHj6BA==; From: Bradley Morgan To: u-boot@lists.u-boot-project.org Cc: trini@konsulko.com, brads@mainlining.org Subject: [PATCH 2/3] doc: arch/powerpc: document the mpc85xx boot images Date: Fri, 30 Oct 2026 01:49:24 +0000 Message-ID: <20261030014925.32610-3-brads@mainlining.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261030014925.32610-1-brads@mainlining.org> References: <20261030014925.32610-1-brads@mainlining.org> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Boards boot from NOR, through a PBL image the BootROM runs, or with a TPL and SPL pair out of NAND, and the image layout changes with each. Write the layouts and the config options that control them down so nobody has to figure it out from the linker scripts again. Signed-off-by: Bradley Morgan --- doc/arch/powerpc/boot.rst | 57 ++++++++++++++++++++++++++++++++++++ doc/arch/powerpc/index.rst | 1 + doc/arch/powerpc/powerpc.rst | 4 ++- 3 files changed, 61 insertions(+), 1 deletion(-) create mode 100644 doc/arch/powerpc/boot.rst diff --git a/doc/arch/powerpc/boot.rst b/doc/arch/powerpc/boot.rst new file mode 100644 index 00000000000..dd01588db18 --- /dev/null +++ b/doc/arch/powerpc/boot.rst @@ -0,0 +1,57 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2026, Bradley Morgan + +Boot images on MPC85xx +====================== + +There are two boot models and the image layout tells you which one you +are dealing with. + +NOR flash +--------- + +U-Boot is linked for CONFIG_TEXT_BASE and u-boot.bin goes straight to +flash. If the SoC has a boot page (CONFIG_MPC85XX_HAVE_RESET_VECTOR), +the reset vector sits at the top of the 4K page, 0xfffffffc. + +With CONFIG_OF_SEPARATE, binman glues u-boot-dtb.bin together using +arch/powerpc/dts/u-boot.dtsi. For a RAM image without a reset vector, +CONFIG_SYS_MPC85XX_NO_RESETVEC throws .resetvec away and moves .bootpg +up. + +RAMBOOT +------- + +RAMBOOT means the BootROM loads the image for you. Depending on the +board that is SD, SPI or NAND, and the defconfig name says which: + +* P2041RDB_SDCARD_defconfig, P2041RDB_SPIFLASH_defconfig +* T1024RDB_SDCARD_defconfig, T1024RDB_SPIFLASH_defconfig, + T1024RDB_NAND_defconfig +* T2080RDB_SDCARD_defconfig, T2080RDB_SPIFLASH_defconfig, + T2080RDB_NAND_defconfig + +These select CONFIG_RAMBOOT_PBL and build a PBL image instead of a plain +u-boot.bin: + +* u-boot.pbl, when U-Boot proper is the only stage +* u-boot-with-spl-pbl.bin, when CONFIG_SPL_FSL_PBL is set and an SPL runs + first + +NAND +---- + +Some P1010 and P1020 boards boot from NAND with a TPL in L2 SRAM that +sets up DDR, then an SPL that loads U-Boot proper. That is the +CONFIG_TPL and CONFIG_SPL_INIT_MINIMAL setup in the _NAND defconfigs. + +SPL builds in general also produce u-boot-with-spl.bin, which is SPL +plus U-Boot proper padded to CONFIG_SPL_PAD_TO. + +SD and SPI, the other way +------------------------- + +The BootROM also handles raw SD and SPI images that carry their own boot +sector. Either let CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR prepend one for +eSDHC, or use the external boot_format tool. See +doc/README.mpc85xx-sd-spi-boot and doc/README.ramboot-ppc85xx. diff --git a/doc/arch/powerpc/index.rst b/doc/arch/powerpc/index.rst index bf0c46b9408..bfeeb1ed2bb 100644 --- a/doc/arch/powerpc/index.rst +++ b/doc/arch/powerpc/index.rst @@ -8,3 +8,4 @@ PowerPC :maxdepth: 2 powerpc + boot diff --git a/doc/arch/powerpc/powerpc.rst b/doc/arch/powerpc/powerpc.rst index 102943383de..1bc5f629ce3 100644 --- a/doc/arch/powerpc/powerpc.rst +++ b/doc/arch/powerpc/powerpc.rst @@ -130,7 +130,8 @@ MPC85xx: See doc/README.mpc85xx-spin-table. * CONFIG_MPC85XX_HAVE_RESET_VECTOR, CONFIG_SYS_MPC85XX_NO_RESETVEC and - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR are the image layout knobs. + CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR are the image layout knobs, they + are explained in :doc:`/arch/powerpc/boot`. Device trees ------------ @@ -157,6 +158,7 @@ No magic here, other architectures do the same. More reading ------------ +* :doc:`/arch/powerpc/boot` * doc/README.pblimage * doc/README.ramboot-ppc85xx * doc/README.mpc85xx-sd-spi-boot -- 2.47.3