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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ae6e2a703esm6590630a91.0.2026.10.29.20.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 20:15:20 -0700 (PDT) From: Chi-Wen Weng To: jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, linux-arm-kernel@lists.infradead.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com, cwweng.linux@gmail.com Subject: [PATCH v3 1/2] dt-bindings: iio: adc: Add Nuvoton MA35D1 EADC Date: Fri, 30 Oct 2026 11:15:00 +0800 Message-Id: <20261030031501.130290-2-cwweng.linux@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261030031501.130290-1-cwweng.linux@gmail.com> References: <20261030031501.130290-1-cwweng.linux@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Chi-Wen Weng Add a devicetree binding for the Enhanced Analog-to-Digital Converter (EADC) found on Nuvoton MA35D1 SoCs. The controller provides eight external analog inputs which can be used as single-ended channels or as four fixed differential pairs: 0-4, 1-5, 2-6 and 3-7. Describe the four hardware interrupt outputs, ADINT0 through ADINT3. ADINT0 through ADINT2 are associated with the corresponding conversion interrupt flags, while ADINT3 is shared by the ADIF3 conversion interrupt and the ADCMPF0 through ADCMPF3 result-compare interrupt sources. Also describe the functional clock, optional reset, optional external reference supply and optional DMA request. Expose the controller as an IIO channel provider through the DT #io-channel-cells property. The cell identifies the logical EADC channel selected by the reg value of the corresponding channel child node. Restrict the channel binding to features supported by the MA35D1 EADC hardware and use the common single-channel representation for single-ended inputs. Signed-off-by: Chi-Wen Weng --- .../bindings/iio/adc/nuvoton,ma35d1-eadc.yaml | 175 ++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/nuvoton,ma35d1-eadc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,ma35d1-eadc.yaml b/Documentation/devicetree/bindings/iio/adc/nuvoton,ma35d1-eadc.yaml new file mode 100644 index 000000000000..97144a8eeb5c --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,ma35d1-eadc.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/nuvoton,ma35d1-eadc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Enhanced Analog-to-Digital Converter + +maintainers: + - Chi-Wen Weng + +description: | + The Nuvoton MA35D1 Enhanced Analog-to-Digital Converter (EADC) is a + 12-bit successive approximation converter with eight external analog + inputs and one internally connected VBAT input. + + The external inputs can be used as eight single-ended channels or as + four fixed differential pairs: 0-4, 1-5, 2-6 and 3-7. The internally + connected VBAT input is not described by a channel child node. + + The controller provides four interrupt outputs, ADINT0 through ADINT3. + ADINT0, ADINT1 and ADINT2 are generated by the corresponding ADIF0, + ADIF1 and ADIF2 conversion interrupt flags. ADINT3 is shared by the + ADIF3 conversion interrupt flag and the ADCMPF0 through ADCMPF3 result + compare flags. + +properties: + compatible: + const: nuvoton,ma35d1-eadc + + reg: + maxItems: 1 + + interrupts: + items: + - description: ADINT0 conversion interrupt output generated by ADIF0 + - description: ADINT1 conversion interrupt output generated by ADIF1 + - description: ADINT2 conversion interrupt output generated by ADIF2 + - description: > + ADINT3 shared interrupt output generated by ADIF3 or by the + ADCMPF0 through ADCMPF3 result compare flags + + interrupt-names: + items: + - const: adint0 + - const: adint1 + - const: adint2 + - const: adint3 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + vref-supply: + description: + Optional external reference voltage connected to the VREF pin. If this + supply is absent, the controller uses its internal 1.6 V reference. + + dmas: + maxItems: 1 + + dma-names: + const: rx + + '#io-channel-cells': + const: 1 + description: + The cell selects the logical EADC channel identified by the reg value + of the corresponding channel child node. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^channel@[0-7]$': + type: object + $ref: /schemas/iio/adc/adc.yaml# + unevaluatedProperties: false + description: | + External EADC channel description. + + For a single-ended channel, single-channel specifies the external + analog input number (0 through 7), while reg provides the logical IIO + channel index. + + For a differential channel, omit single-channel. The reg value selects + one of the four fixed hardware differential pairs: reg 0 selects 0-4, + reg 1 selects 1-5, reg 2 selects 2-6 and reg 3 selects 3-7. + + properties: + reg: + maximum: 7 + + single-channel: + maximum: 7 + + # Differential pairs are fixed in hardware and are selected by reg. + diff-channels: false + + bipolar: false + + common-mode-channel: false + + settling-time-us: false + + oversampling-ratio: false + + allOf: + - if: + not: + required: + - single-channel + then: + properties: + reg: + maximum: 3 + + required: + - reg + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - '#io-channel-cells' + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + adc@40430000 { + compatible = "nuvoton,ma35d1-eadc"; + reg = <0x0 0x40430000 0x0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "adint0", "adint1", "adint2", "adint3"; + clocks = <&clk EADC_GATE>; + resets = <&reset MA35D1_RESET_EADC0>; + + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + single-channel = <0>; + }; + + channel@1 { + reg = <1>; + }; + }; + }; + +... -- 2.25.1