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Fri, 30 Oct 2026 07:30:48 +0000 (UTC) Received: from laptop.redhat.corp (headnet04.pony-001.prod.iad2.dc.redhat.com [10.2.32.116]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 4307730001A4; Fri, 30 Oct 2026 07:30:43 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, richard.henderson@linaro.org, pbonzini@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com, 7746591750@163.com, maobibo@loongson.cn, harshpb@linux.ibm.com, amachhiw@linux.ibm.com, daniel.barboza@oss.qualcomm.com, milesg@linux.ibm.com, farman@linux.ibm.com, cohuck@redhat.com, alireza.sanaee@huawei.com Cc: armbru@redhat.com, mbawa@redhat.com Subject: [PATCH v3 for-11.2 08/10] hw/arm/virt: Make sure virt_get_caches() keeps on reading CLIDR_EL1 as 0 Date: Fri, 30 Oct 2026 08:28:49 +0100 Message-ID: <20261030072956.402425-9-eric.auger@redhat.com> In-Reply-To: <20261030072956.402425-1-eric.auger@redhat.com> References: <20261030072956.402425-1-eric.auger@redhat.com> X-Archived-By: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 X-Mimecast-MFC-PROC-ID: SDsmxc9FAjKShOO-oxmCIrMHa_H1ykN02RIPrcxJyMg_1793345448 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit content-type: text/plain; charset="US-ASCII"; x-default=true Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 5 X-Spam_score: 0.5 X-Spam_bar: / X-Spam_report: (0.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 In KVM mode, virt_get_caches() currently gets a zero value for the CLIDR_EL1 register. This is due to the fact CLIDR is never read from host. This is a bug. Soon we will initialize all writable isar.idreg[] from host and this includes CLIDR_EL1. However, we cannot directly fix the initialization, first because it would change the way caches are exposed to guest in DT/ACPI descriptions and because some host values would be rejected by the current QEMU code, especially in the case host has a unified L1 cache which is currently not supported and triggers the following error: "Unified type is not implemented at level 1" error. So this issue will be fixed separately. Signed-off-by: Eric Auger Reviewed-by: Khushit Shah Reviewed-by: Gustavo Romero Reviewed-by: Mohammadfaiz Bawa --- v1 -> v2: - fix the commit msg and improved comment (Gustavo) --- hw/arm/virt.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 0d56197dac..a80c60f3fa 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -338,6 +338,21 @@ unsigned int virt_get_caches(const VirtMachineState *vms, CPUCoreCaches *caches) ARMISARegisters *isar = &armcpu->isar; uint32_t clidr = GET_IDREG(isar, CLIDR); + /* + * Commit f669de70011 ("hw/arm/virt: add cache hierarchy to device tree") + * read the CLIDR value from the isar array. However, in KVM mode, we failed + * to initialize that register value from host and the resulting bug is that + * we have always read 0. + * + * Soon we will initialize all writable isar.idreg[] from host, including + * CLIDR_EL1 but we will need to handle compat properly and also extend the + * support to unified L1 cache. For now do not pretend we have something + * different from 0. + */ + if (kvm_enabled()) { + clidr = 0; + } + for (int cache_level = 1; cache_level <= CLIDR_CTYPE_MAX_CACHE_LEVEL; cache_level++) { uint8_t ctype = -- 2.53.0