From: Thierry Reding <thierry.reding@kernel.org>
To: Thierry Reding <thierry.reding@kernel.org>,
Jon Hunter <jonathanh@nvidia.com>,
Mikko Perttunen <mperttunen@nvidia.com>
Cc: Sumit Gupta <sumitg@nvidia.com>,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: [PATCH 3/3] arm64: tegra: Remove PCI ranges from VISION chiplet
Date: Fri, 30 Oct 2026 15:11:01 +0100 [thread overview]
Message-ID: <20261030141101.845044-3-thierry.reding@kernel.org> (raw)
In-Reply-To: <20261030141101.845044-1-thierry.reding@kernel.org>
From: Thierry Reding <treding@nvidia.com>
The VISION chiplet doesn't have any PCI controllers and therefore
doesn't need PCI related ranges for address translation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index ea2e9adff6d9..b7f6b649baab 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3996,9 +3996,7 @@ bus@8180000000 {
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0x000 0x00000000 0x81 0x80000000 0x00 0x10000000>, /* MMIO (256 MiB) */
- <0x100 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */
- <0x200 0x00000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
+ ranges = <0x000 0x00000000 0x81 0x80000000 0x00 0x10000000>; /* MMIO (256 MiB) */
host1x@1200000 {
compatible = "nvidia,tegra264-host1x";
--
2.55.0
prev parent reply other threads:[~2026-10-30 14:11 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-30 14:10 [PATCH 1/3] arm64: tegra: Fix address translation on Tegra264 Thierry Reding
2026-10-30 14:11 ` [PATCH 2/3] arm64: tegra: Fix memory size unit in comment Thierry Reding
2026-10-30 14:11 ` Thierry Reding [this message]
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