drivers/clk/renesas/rzg2l-cpg.c:1222:52-58: opportunity for str_enable_disable(enable)

[kernel test robot <lkp@intel.com>]

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
CC: linux-kernel@vger.kernel.org
TO: Biju Das <biju.das.jz@bp.renesas.com>
CC: Geert Uytterhoeven <geert+renesas@glider.be>

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   d89e1d186ec9271bf78e62771779e9fc03bf0fc3
commit: 78db1faa6b681da20ec167268b28778ebb0f98b7 clk: renesas: rzg2l: Add support for enabling PLLs
date:   6 months ago
:::::: branch date: 15 hours ago
:::::: commit date: 6 months ago
config: mips-randconfig-r2109-20261030 (https://download.01.org/0day-ci/archive/20261030/202610301526.XkacnSyK-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Fixes: 78db1faa6b68 ("clk: renesas: rzg2l: Add support for enabling PLLs")
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Julia Lawall <julia.lawall@inria.fr>
| Closes: https://lore.kernel.org/r/202610301526.XkacnSyK-lkp@intel.com/

cocci warnings: (new ones prefixed by >>)
>> drivers/clk/renesas/rzg2l-cpg.c:1222:52-58: opportunity for str_enable_disable(enable)

vim +1222 drivers/clk/renesas/rzg2l-cpg.c

78db1faa6b681d Biju Das 2026-03-26  1195  
78db1faa6b681d Biju Das 2026-03-26  1196  static int rzg3l_cpg_pll_clk_endisable(struct clk_hw *hw, bool enable)
78db1faa6b681d Biju Das 2026-03-26  1197  {
78db1faa6b681d Biju Das 2026-03-26  1198  	struct pll_clk *pll_clk = to_pll(hw);
78db1faa6b681d Biju Das 2026-03-26  1199  	struct rzg2l_cpg_priv *priv = pll_clk->priv;
78db1faa6b681d Biju Das 2026-03-26  1200  	u32 stby_offset, mon_offset;
78db1faa6b681d Biju Das 2026-03-26  1201  	u32 val, mon_val;
78db1faa6b681d Biju Das 2026-03-26  1202  	int ret;
78db1faa6b681d Biju Das 2026-03-26  1203  
78db1faa6b681d Biju Das 2026-03-26  1204  	stby_offset = RZG3L_PLL_STBY_OFFSET(pll_clk->conf);
78db1faa6b681d Biju Das 2026-03-26  1205  	mon_offset = RZG3L_PLL_MON_OFFSET(pll_clk->conf);
78db1faa6b681d Biju Das 2026-03-26  1206  
78db1faa6b681d Biju Das 2026-03-26  1207  	if (enable) {
78db1faa6b681d Biju Das 2026-03-26  1208  		val = RZG3L_PLL_STBY_RESETB_WEN | RZG3L_PLL_STBY_RESETB;
78db1faa6b681d Biju Das 2026-03-26  1209  		mon_val = RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK;
78db1faa6b681d Biju Das 2026-03-26  1210  	} else {
78db1faa6b681d Biju Das 2026-03-26  1211  		val = RZG3L_PLL_STBY_RESETB_WEN;
78db1faa6b681d Biju Das 2026-03-26  1212  		mon_val = 0;
78db1faa6b681d Biju Das 2026-03-26  1213  	}
78db1faa6b681d Biju Das 2026-03-26  1214  
78db1faa6b681d Biju Das 2026-03-26  1215  	writel(val, priv->base + stby_offset);
78db1faa6b681d Biju Das 2026-03-26  1216  
78db1faa6b681d Biju Das 2026-03-26  1217  	/* ensure PLL is in normal/standby mode */
78db1faa6b681d Biju Das 2026-03-26  1218  	ret = readl_poll_timeout_atomic(priv->base + mon_offset, val, mon_val ==
78db1faa6b681d Biju Das 2026-03-26  1219  					(val & (RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK)),
78db1faa6b681d Biju Das 2026-03-26  1220  					10, 100);
78db1faa6b681d Biju Das 2026-03-26  1221  	if (ret)
78db1faa6b681d Biju Das 2026-03-26 @1222  		dev_err(priv->dev, "Failed to %s PLL 0x%x/%pC\n", enable ?
78db1faa6b681d Biju Das 2026-03-26  1223  			"enable" : "disable", stby_offset, hw->clk);
78db1faa6b681d Biju Das 2026-03-26  1224  
78db1faa6b681d Biju Das 2026-03-26  1225  	return ret;
78db1faa6b681d Biju Das 2026-03-26  1226  }
78db1faa6b681d Biju Das 2026-03-26  1227  

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