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Fri, 30 Oct 2026 12:50:30 -0700 (PDT) Received: from munique-a520 ([2804:3bf0:fe29:ac41:2d94:706:4bfd:852e]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5ec69bf34c0sm3449419e0c.8.2026.10.30.12.50.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 12:50:29 -0700 (PDT) From: Munique Feitoza To: Basavaraj Natikar , Shyam Sundar S K , Linus Walleij Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Munique Feitoza Subject: [PATCH] pinctrl: amd: Clear interrupt enable on spurious IRQ and skip unhandled EOI Date: Fri, 30 Oct 2026 16:50:25 -0300 Message-ID: <20261030195025.5153-1-muniquefeitoz4@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When do_amd_gpio_irq_handler() detects a spurious interrupt on a pin that is not configured as an IRQ line (!gpiochip_line_is_irq()), it currently only clears BIT(INTERRUPT_MASK_OFF) while leaving BIT(INTERRUPT_ENABLE_OFF) set. Unlike amd_gpio_irq_disable(), leaving INTERRUPT_ENABLE_OFF enabled allows the pin status bit to keep re-asserting in WAKE_INT_STATUS_REG0/1. Clear both INTERRUPT_MASK_OFF and INTERRUPT_ENABLE_OFF when disabling a spurious GPIO IRQ on both main and RGPIO banks. Additionally, if no GPIO interrupt was handled (ret == false), return early before acquiring gpio_dev->lock and writing EOI_MASK to WAKE_INT_MASTER_REG. This avoids unnecessary MMIO accesses and spinlock contention when the IRQ line is shared or asserted by an unhandled spurious interrupt storm. Signed-off-by: Munique Feitoza --- drivers/pinctrl/pinctrl-amd.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 9fa752f55..428440949 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -671,7 +671,8 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) raw_spin_lock_irqsave(&gpio_dev->lock, flags); regval = readl(amd_gpio_pin_reg(gpio_dev, irqnr + i)); if (!gpiochip_line_is_irq(gc, irqnr + i)) { - regval &= ~BIT(INTERRUPT_MASK_OFF); + regval &= ~(BIT(INTERRUPT_MASK_OFF) | + BIT(INTERRUPT_ENABLE_OFF)); dev_dbg(&gpio_dev->pdev->dev, "Disabling spurious GPIO IRQ %d\n", irqnr + i); @@ -722,7 +723,8 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) raw_spin_lock_irqsave(&gpio_dev->lock, flags); regval = readl(amd_gpio_pin_reg(gpio_dev, pin)); if (!gpiochip_line_is_irq(gc, pin)) { - regval &= ~BIT(INTERRUPT_MASK_OFF); + regval &= ~(BIT(INTERRUPT_MASK_OFF) | + BIT(INTERRUPT_ENABLE_OFF)); dev_dbg(&gpio_dev->pdev->dev, "Disabling spurious GPIO IRQ %d\n", pin); @@ -735,7 +737,7 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) } /* did not cause wake on resume context for shared IRQ */ - if (irq < 0) + if (irq < 0 || !ret) return false; /* Signal EOI to the GPIO unit */ -- 2.56.0