Re: [PATCH v5] drm/xe/cri: Implement Wa_14028586678

[Matt Roper <matthew.d.roper@intel.com>]

On Fri, Oct 30, 2026 at 01:19:08PM -0700, Daniel Charles wrote:
> From: Fei Yang <fei.yang@intel.com>
> 
> Implement the documented Wa_14028586678 hardware workaround on
> Crescent Island by updating the L3 class-of-service and caching-policy
> fields in DWNSTRM_ACCESS_MODE (0x144154). Change bits [7:4] from 0x3
> to 0xc to select L3 class of service 3 and write-back caching, while
> preserving the other register fields.
> 
> v2:
>   - Move this workaround into a dedicated MERT table instead of
>     placing it in gt_was, since MERT registers are device-level and
>     accessed through root-tile MMIO, outside GT forcewake and GT
>     save/restore bookkeeping.
>   - Add an RTP helper for full-register device MMIO writes and apply
>     the MERT table during probe and after pcode is ready on system or
>     D3cold resume. Match Crescent Island and skip devices without MERT
>     and SR-IOV VFs.
> 
> v3:
>   - Use PLATFORM(CRESCENTISLAND) instead of GRAPHICS_VERSION(3511),
>     because device-level OOB processing has no GT context and the
>     graphics-version matcher requires one.
> 
> v4:
>   - Switching from RTP to OOB removes the need for the MERT-specific
>     table and RTP helper proposed in v2. The v2 and v3 notes are retained
>     as revision history; this version uses the device OOB rule through
>     the existing per-tile workaround helper.
>   - Program the register on every tile, assuming the workaround values
>     are identical across tiles.
>   - Use a masked read-modify-write to set [7:6] to 0x3 and [5:4] to
>     0x0, preserving all other register fields.
> v5:
>   - Apply tile workarounds after PCODE initialization completes on system
>     resume, matching the runtime resume ordering.
> 
> BSpec: 73603
> Signed-off-by: Fei Yang <fei.yang@intel.com>
> Signed-off-by: Daniel Charles <daniel.charles@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_mert_regs.h    |  4 ++++
>  drivers/gpu/drm/xe/xe_device_wa_oob.rules |  1 +
>  drivers/gpu/drm/xe/xe_pm.c                | 10 +++++++---
>  drivers/gpu/drm/xe/xe_wa.c                |  9 +++++++++
>  4 files changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
> index 99e5a26da6572..8139263f2746a 100644
> --- a/drivers/gpu/drm/xe/regs/xe_mert_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
> @@ -8,6 +8,10 @@
>  
>  #include "regs/xe_reg_defs.h"
>  
> +#define DWNSTRM_ACCESS_MODE_GAMREQ_MERTSS	XE_REG(0x144154)
> +#define   DWNSTRM_ACCESS_MODE_L3_COS		REG_GENMASK(7, 6)

This should probably be "CLOS" instead of "COS" to match the name in the
bspec and way "class of service" is abbreviated elsewhere in the driver.

> +#define   DWNSTRM_ACCESS_MODE_L3_POLICY		REG_GENMASK(5, 4)
> +
>  #define MERT_LMEM_CFG				XE_REG(0x1448b0)
>  
>  #define MERT_TLB_CT_INTR_ERR_ID_PORT		XE_REG(0x145190)
> diff --git a/drivers/gpu/drm/xe/xe_device_wa_oob.rules b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
> index 356b4707dafea..753b2a4a10067 100644
> --- a/drivers/gpu/drm/xe/xe_device_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
> @@ -6,3 +6,4 @@
>  14026633728	PLATFORM(CRESCENTISLAND)
>  14026746987	PLATFORM(CRESCENTISLAND)
>  14026779378	PLATFORM(CRESCENTISLAND)
> +14028586678	PLATFORM(CRESCENTISLAND)
> diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
> index 89d64aa6577d1..462357844cb48 100644
> --- a/drivers/gpu/drm/xe/xe_pm.c
> +++ b/drivers/gpu/drm/xe/xe_pm.c
> @@ -241,13 +241,13 @@ int xe_pm_resume(struct xe_device *xe)
>  	drm_dbg(&xe->drm, "Resuming device\n");
>  	trace_xe_pm_resume(xe, __builtin_return_address(0));
>  
> -	for_each_tile(tile, xe, id)
> -		xe_wa_apply_tile_workarounds(tile);
> -
>  	err = xe_pcode_ready(xe, true);
>  	if (err)
>  		return err;
>  
> +	for_each_tile(tile, xe, id)
> +		xe_wa_apply_tile_workarounds(tile);
> +

The ordering change and extra call in runtime resume below aren't part
of the workaround itself; they're general changes to existing driver
logic so they should be in a separate patch with a dedicated commit
message explaining the reasoning (and that patch should probably be have
Fixes: for the commit that added the tile workaround code originally).

>  	for_each_gt(gt, xe, id)
>  		xe_gt_resume_early(gt);
>  
> @@ -687,6 +687,7 @@ int xe_pm_runtime_suspend(struct xe_device *xe)
>   */
>  int xe_pm_runtime_resume(struct xe_device *xe)
>  {
> +	struct xe_tile *tile;
>  	struct xe_gt *gt;
>  	u8 id;
>  	int err = 0;
> @@ -702,6 +703,9 @@ int xe_pm_runtime_resume(struct xe_device *xe)
>  		if (err)
>  			goto out;
>  
> +		for_each_tile(tile, xe, id)
> +			xe_wa_apply_tile_workarounds(tile);
> +
>  		for_each_gt(gt, xe, id)
>  			xe_gt_resume_early(gt);
>  
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index c94fe7753f9a9..539850614902b 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -16,7 +16,9 @@
>  #include "regs/xe_engine_regs.h"
>  #include "regs/xe_gt_regs.h"
>  #include "regs/xe_guc_regs.h"
> +#include "regs/xe_mert_regs.h"
>  #include "regs/xe_regs.h"
> +#include "xe_device.h"
>  #include "xe_device_types.h"
>  #include "xe_force_wake.h"
>  #include "xe_gt_types.h"
> @@ -1031,4 +1033,11 @@ void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
>  
>  	if (XE_DEVICE_WA(tile->xe, 22010954014))
>  		xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
> +
> +	if (xe_device_has_mert(tile->xe) &&

We don't need the 'has_mert' check; this workaround lineage number will
already only be associated with platforms that have MERT.


Matt

> +	    XE_DEVICE_WA(tile->xe, 14028586678))
> +		xe_mmio_rmw32(mmio, DWNSTRM_ACCESS_MODE_GAMREQ_MERTSS,
> +			      DWNSTRM_ACCESS_MODE_L3_COS |
> +			      DWNSTRM_ACCESS_MODE_L3_POLICY,
> +			      REG_FIELD_PREP(DWNSTRM_ACCESS_MODE_L3_COS, 3));
>  }
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation