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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id 5614622812f47-5640fd93451sm2821127b6e.3.2026.10.30.19.27.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 19:27:00 -0700 (PDT) From: Enzo Adriano To: Andre Przywara Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Ulf Hansson , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Subject: Re: [PATCH 3/4] arm64: dts: allwinner: add Allwinner A733 SoC Date: Fri, 30 Oct 2026 22:26:59 -0400 Message-ID: <20261031020640-263f7b05-a7s-reply@gmail.com> In-Reply-To: <20260911001805.0a2e033d@ryzen.lan> References: <20260613-a733-dts-v1-public-ready-v1-0-7787c94681db@gmail.com> <20260613-a733-dts-v1-public-ready-v1-3-7787c94681db@gmail.com> <20260911001805.0a2e033d@ryzen.lan> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Hi Andre, The v2 cover is Message-ID: <20261031020640-263f7b05-a7s-dt-v2-0@gmail.com> I have incorporated your review into the three-patch DT v2. The initial SoC description now includes the RTC, all UART and main/R I2C instances, R-PIO/R-CCU, all four MMC controllers, and the documented pin groups. The board enables UART0, the AXP318W on R-I2C0 and the microSD slot. On the individual points: * Base/checks: the series uses official base d89e1d186ec9271bf78e62771779e9fc03bf0fc3 with the exact public clock, PMIC, pinctrl and UART dependencies listed in the cover letter. The full ARM64 dtbs target and final A7S W=2 CHECK_DTBS=y check pass. * RTC: added with its current clock inputs and the board's 32768 Hz source. RTC counter advancement was exercised on the board. * PSCI/timers: removed arm,psci-1.0 and added the ARMv8.2 EL2 virtual timer interrupt, PPI 12. The redundant disabled-by-default prose is gone. * Pins/UARTs: added explicit pinmux values, MMC1/2/3 pin groups and all seven main plus two R UARTs. UART0's pins are in the DTSI. * GIC: added maintenance PPI 9 and the ITS at 0x03440000/0x20000. GIC/ITS dma-noncoherent follows your public A733 reference and the A523 precedent; the CPUX interconnect diagram supports that integration inference. ITS remains disabled; MSI and EL2 delivery are not claimed. * MMC: all four controllers are described. MMC0-2 retain the existing A733/D1 binding. SMHC3 has different DES0/high-address fields and a 12-bit DES1 length, so I gave it a separate binding and compatible instead of claiming D1 programming compatibility. That node remains disabled; no operational eMMC driver is claimed. * I2C/PMIC/R-domain: added all 13 main and three R I2C nodes, R-PIO and R-CCU. R-I2C0 and AXP318W are enabled, with schematic-derived PMIC inputs/outputs, CPU supplies and pin supplies. The microSD slot uses SWOUT2 and PF6 active-high card detect with a pull-down. Three supporting changes are separate from the DT series: firmware clock preservation, A733 main/R pinctrl voltage-mode preservation, and the distinct MMC3 binding. The pinctrl approach follows Vinicius's October 14 recommendation. The clock/binding prerequisites should land through their respective trees before the dependent DT changes. Two final-candidate Cubie A7S RAM boots passed, including eight CPUs, PMIC/I2C activity, RTC advancement, UART baud changes, 148 MiB of read-only SD traffic per boot at 50 MHz/four bits/3.3 V, and warm reboot. The second run crossed the late unused-regulator shutdown boundary. The tests used vendor boot firmware and a RAM-only BL31 reservation. They do not claim card writes/hotplug/UHS, operation of the other controllers, RTC alarms, or EL2/ITS/MSI functionality. One electrical uncertainty is explicit: the schematic's nominal 2.4 V BLDO input conflicts with the software-reported 3.3 V BLDO2 selector. Physical measurements are unavailable. The DT preserves the existing setting without a voltage constraint or newly enabled LVDS consumer. Resolving the physical voltage requires inspecting RP220/RP298/RP299 and measuring UP11 LDO2V5-INPUT and BLDO2/VCC-LVDS0 to ground. The acknowledged board binding is retained, the old MMC binding already in the selected base is not resubmitted, and the oscillator names, 26 MHz board crystal, four CCU inputs and DTB ordering are corrected. AI assistance is disclosed as Codex:gpt-6-astra, with Assisted-by: LLM retained in the patches. Thanks, Enzo