From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03934606A31A for ; Sat, 31 Oct 2026 06:59:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key, unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=PxTvU1Ia Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xN337-0002a5-LI; Sat, 31 Oct 2026 02:58:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xN336-0002ZQ-H0 for qemu-arm@nongnu.org; Sat, 31 Oct 2026 02:58:44 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xN334-0002iH-P7 for qemu-arm@nongnu.org; Sat, 31 Oct 2026 02:58:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1793429922; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zgKn23hka7jh3uCBga/nzamCa7BNiyL3QaJJMe6IKYk=; b=PxTvU1IaHKPSYZGx+mE6Qs5F8QlZ8ZXRYFijg8Ms1PhjBGYgVlYCdyoZep61GUpFe9u65M psEV7l9+YW3TBIn9rsltCiTi9ADTYGmpUqE6NLOvDjreY8mCyVhRvKe5Kva0Z4siJcrDJX SbRBemqA1r5K8adT/fgn9H53D6SkDvk= Received: from mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-158-k6eFy55xMU-w6ZxMNIWxuQ-1; Sat, 31 Oct 2026 02:58:38 -0400 X-MC-Unique: k6eFy55xMU-w6ZxMNIWxuQ-1 X-Mimecast-MFC-AGG-ID: k6eFy55xMU-w6ZxMNIWxuQ_1793429917 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 2286D19560B4; Sat, 31 Oct 2026 06:58:37 +0000 (UTC) Received: from circe.redhat.com (unknown [10.44.32.2]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 6D11D1803A40; Sat, 31 Oct 2026 06:58:35 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 01/34] hw/ssi/aspeed_smc: Fix AST2700 segment end address decoding Date: Sat, 31 Oct 2026 07:57:50 +0100 Message-ID: <20261031065823.191966-2-clg@redhat.com> In-Reply-To: <20261031065823.191966-1-clg@redhat.com> References: <20261031065823.191966-1-clg@redhat.com> X-Archived-By: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 X-Mimecast-MFC-PROC-ID: cCLDEOJxxpIhpRaBFv_z3hv5ASifTInQXV5-wTB7G4g_1793429917 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 5 X-Spam_score: 0.5 X-Spam_bar: / X-Spam_report: (0.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Jamin Lin The AST2700 Address Decoding Range Registers (SPI030 - SPI03C) define the end address as an exclusive upper bound, with a unit of 64KB: StartAdr <= CEx < EndAdr When the start address equals the end address, the decoding is disabled. However, aspeed_2700_smc_segment_to_reg() and aspeed_2700_smc_reg_to_segment() treat the end address as inclusive. The end offset is programmed as (addr + size - 1) and an extra 64KB is added back when decoding it. As a result, every segment is 64KB larger than the range defined by the register and overlaps the next chip select. The issue can be reproduced by booting an AST2700 ASPEED SDK image with "-d guest_errors", which reports a lot of segment overlap errors such as: aspeed_smc_flash_set_segment: new segment for CS0 is not aligned : [ 0x100000000 - 0x108010000 ] aspeed_smc_flash_overlap: new segment CS1 [ 0x108000000 - 0x110010000 ] overlaps with CS0 [ 0x100000000 - 0x108010000 ] Fix the segment helpers to use an exclusive end address, so that the decoded segments match the definition in the AST2700 datasheet. Fixes: bdb3748dba30 ("aspeed/smc: Add AST2700 support") Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/20261028023154.48395-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater --- hw/ssi/aspeed_smc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index bf596f7b2d68..10ea9e5aa063 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -1823,7 +1823,7 @@ static uint32_t aspeed_2700_smc_segment_to_reg(const AspeedSMCState *s, } reg |= (seg->addr & AST2700_SEG_ADDR_MASK) >> 16; /* start offset */ - reg |= (seg->addr + seg->size - 1) & AST2700_SEG_ADDR_MASK; /* end offset */ + reg |= (seg->addr + seg->size) & AST2700_SEG_ADDR_MASK; /* end offset */ return reg; } @@ -1836,7 +1836,7 @@ static void aspeed_2700_smc_reg_to_segment(const AspeedSMCState *s, if (reg) { seg->addr = asc->flash_window_base + start_offset; - seg->size = end_offset + (64 * KiB) - start_offset; + seg->size = end_offset - start_offset; } else { seg->addr = asc->flash_window_base; seg->size = 0; -- 2.56.0