From: Michael Gur <michaelgur@nvidia.com>
To: jgg@ziepe.ca, leon@kernel.org, linux-rdma@vger.kernel.org
Cc: Edward Srouji <edwards@nvidia.com>,
Yishai Hadas <yishaih@nvidia.com>,
Michael Gur <michaelgur@nvidia.com>,
Jason Gunthorpe <jgg@nvidia.com>,
Saeed Mahameed <saeedm@nvidia.com>,
Tariq Toukan <tariqt@nvidia.com>, Mark Bloch <mbloch@nvidia.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@kernel.org>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Dragos Tatulea <dtatulea@nvidia.com>,
Cosmin Ratiu <cratiu@nvidia.com>, Gal Pressman <gal@nvidia.com>,
linux-kernel@vger.kernel.org (open list),
netdev@vger.kernel.org (open list:MELLANOX MLX5 core VPI driver)
Subject: [PATCH rdma-next v2 05/15] mlx5: Rename IFC bits of relaxed ordering fields
Date: Tue, 3 Nov 2026 00:32:58 +0200 [thread overview]
Message-ID: <20261102223325.2115128-6-michaelgur@nvidia.com> (raw)
In-Reply-To: <20261102223325.2115128-1-michaelgur@nvidia.com>
Align the IFC field names with the new naming:
- relaxed_ordering_write_umr -> order_write_after_write_umr (cap)
- relaxed_ordering_read_umr -> pci_relaxed_ordered_read_umr (cap)
- relaxed_ordering_write -> mkc_order_write_after_write_ro (cap)
- relaxed_ordering_write -> order_write_after_write (mkc)
- relaxed_ordering_read -> pci_relaxed_ordered_read (cap and mkc)
Update all references across drivers.
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Yishai Hadas <yishaih@nvidia.com>
Signed-off-by: Michael Gur <michaelgur@nvidia.com>
---
drivers/infiniband/hw/mlx5/mr.c | 16 ++++++++--------
drivers/infiniband/hw/mlx5/umr.c | 14 +++++++-------
drivers/infiniband/hw/mlx5/umr.h | 8 ++++----
.../ethernet/mellanox/mlx5/core/data_direct.c | 8 ++++----
.../net/ethernet/mellanox/mlx5/core/en/params.c | 2 +-
.../net/ethernet/mellanox/mlx5/core/en_common.c | 8 ++++----
include/linux/mlx5/mlx5_ifc.h | 12 ++++++------
7 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
index 176f87ba062c..a15610c6211c 100644
--- a/drivers/infiniband/hw/mlx5/mr.c
+++ b/drivers/infiniband/hw/mlx5/mr.c
@@ -71,14 +71,14 @@ static void set_mkc_access_pd_addr_fields(void *mkc, int acc, u64 start_addr,
MLX5_SET(mkc, mkc, lr, 1);
if (acc & IB_ACCESS_RELAXED_ORDERING) {
- if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write))
- MLX5_SET(mkc, mkc, relaxed_ordering_write, 1);
+ if (MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro))
+ MLX5_SET(mkc, mkc, order_write_after_write, 1);
- if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) ||
+ if (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) ||
(MLX5_CAP_GEN(dev->mdev,
relaxed_ordering_read_pci_enabled) &&
pcie_relaxed_ordering_enabled(dev->mdev->pdev)))
- MLX5_SET(mkc, mkc, relaxed_ordering_read, 1);
+ MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, 1);
}
MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
@@ -146,14 +146,14 @@ static int get_unchangeable_access_flags(struct mlx5_ib_dev *dev,
ret |= IB_ACCESS_REMOTE_ATOMIC;
if ((access_flags & IB_ACCESS_RELAXED_ORDERING) &&
- MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) &&
- !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
+ MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro) &&
+ !MLX5_CAP_GEN(dev->mdev, order_write_after_write_umr))
ret |= IB_ACCESS_RELAXED_ORDERING;
if ((access_flags & IB_ACCESS_RELAXED_ORDERING) &&
- (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) ||
+ (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) ||
MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled)) &&
- !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
+ !MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read_umr))
ret |= IB_ACCESS_RELAXED_ORDERING;
return ret;
diff --git a/drivers/infiniband/hw/mlx5/umr.c b/drivers/infiniband/hw/mlx5/umr.c
index 711075e3d9ea..144cf851c41e 100644
--- a/drivers/infiniband/hw/mlx5/umr.c
+++ b/drivers/infiniband/hw/mlx5/umr.c
@@ -59,10 +59,10 @@ static __be64 get_umr_update_access_mask(struct mlx5_ib_dev *dev)
if (MLX5_CAP_GEN(dev->mdev, atomic))
result |= MLX5_MKEY_MASK_A;
- if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
+ if (MLX5_CAP_GEN(dev->mdev, order_write_after_write_umr))
result |= MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE;
- if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
+ if (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read_umr))
result |= MLX5_MKEY_MASK_RELAXED_ORDERING_READ;
return cpu_to_be64(result);
@@ -88,11 +88,11 @@ static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
return -EPERM;
if (mask & MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE &&
- !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
+ !MLX5_CAP_GEN(dev->mdev, order_write_after_write_umr))
return -EPERM;
if (mask & MLX5_MKEY_MASK_RELAXED_ORDERING_READ &&
- !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
+ !MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read_umr))
return -EPERM;
return 0;
@@ -446,7 +446,7 @@ static void mlx5r_umr_set_access_flags(struct mlx5_ib_dev *dev,
unsigned int access_flags)
{
bool ro_read = (access_flags & IB_ACCESS_RELAXED_ORDERING) &&
- (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) ||
+ (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) ||
pcie_relaxed_ordering_enabled(dev->mdev->pdev));
MLX5_SET(mkc, seg, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
@@ -454,9 +454,9 @@ static void mlx5r_umr_set_access_flags(struct mlx5_ib_dev *dev,
MLX5_SET(mkc, seg, rr, !!(access_flags & IB_ACCESS_REMOTE_READ));
MLX5_SET(mkc, seg, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE));
MLX5_SET(mkc, seg, lr, 1);
- MLX5_SET(mkc, seg, relaxed_ordering_write,
+ MLX5_SET(mkc, seg, order_write_after_write,
!!(access_flags & IB_ACCESS_RELAXED_ORDERING));
- MLX5_SET(mkc, seg, relaxed_ordering_read, ro_read);
+ MLX5_SET(mkc, seg, pci_relaxed_ordered_read, ro_read);
}
int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd,
diff --git a/drivers/infiniband/hw/mlx5/umr.h b/drivers/infiniband/hw/mlx5/umr.h
index bda7123781a9..04dec726b267 100644
--- a/drivers/infiniband/hw/mlx5/umr.h
+++ b/drivers/infiniband/hw/mlx5/umr.h
@@ -61,14 +61,14 @@ static inline bool mlx5r_umr_can_reconfig(struct mlx5_ib_dev *dev,
return false;
if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&
- MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) &&
- !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
+ MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro) &&
+ !MLX5_CAP_GEN(dev->mdev, order_write_after_write_umr))
return false;
if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&
- (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) ||
+ (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) ||
MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled)) &&
- !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
+ !MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read_umr))
return false;
return true;
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/data_direct.c b/drivers/net/ethernet/mellanox/mlx5/core/data_direct.c
index 5afb11a2a9f0..b2eb2cb0d734 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/data_direct.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/data_direct.c
@@ -145,13 +145,13 @@ static int mlx5_data_direct_create_resources(struct mlx5_core_dev *mdev)
mdev->data_direct->pdn = pdn;
/* create another mkey with RO support */
- if (MLX5_CAP_GEN(mdev, relaxed_ordering_write)) {
- MLX5_SET(mkc, mkc, relaxed_ordering_write, 1);
+ if (MLX5_CAP_GEN(mdev, mkc_order_write_after_write_ro)) {
+ MLX5_SET(mkc, mkc, order_write_after_write, 1);
ro_supp = true;
}
- if (MLX5_CAP_GEN(mdev, relaxed_ordering_read)) {
- MLX5_SET(mkc, mkc, relaxed_ordering_read, 1);
+ if (MLX5_CAP_GEN(mdev, pci_relaxed_ordered_read)) {
+ MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, 1);
ro_supp = true;
}
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c
index 5caf7820a136..b0fc1fdd1339 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c
@@ -912,7 +912,7 @@ static void mlx5e_build_rx_cq_param(struct mlx5_core_dev *mdev,
static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
{
bool lro_en = params->packet_merge.type == MLX5E_PACKET_MERGE_LRO;
- bool ro = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
+ bool ro = MLX5_CAP_GEN(mdev, mkc_order_write_after_write_ro);
return ro && lro_en ?
MLX5_WQ_END_PAD_MODE_NONE : MLX5_WQ_END_PAD_MODE_ALIGN;
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c
index c2d4bae533de..2dbcf6673916 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c
@@ -40,13 +40,13 @@
void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
{
- bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
- bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read) ||
+ bool ro_write = MLX5_CAP_GEN(mdev, mkc_order_write_after_write_ro);
+ bool ro_read = MLX5_CAP_GEN(mdev, pci_relaxed_ordered_read) ||
(pcie_relaxed_ordering_enabled(mdev->pdev) &&
MLX5_CAP_GEN(mdev, relaxed_ordering_read_pci_enabled));
- MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_read);
- MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_write);
+ MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, ro_read);
+ MLX5_SET(mkc, mkc, order_write_after_write, ro_write);
}
int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey)
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 697fc9387b73..8531d611fa9b 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1711,15 +1711,15 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 max_sgl_for_optimized_performance[0x8];
u8 log_max_cq_sz[0x8];
- u8 relaxed_ordering_write_umr[0x1];
- u8 relaxed_ordering_read_umr[0x1];
+ u8 order_write_after_write_umr[0x1];
+ u8 pci_relaxed_ordered_read_umr[0x1];
u8 reserved_at_d2[0x7];
u8 virtio_net_device_emualtion_manager[0x1];
u8 virtio_blk_device_emualtion_manager[0x1];
u8 log_max_cq[0x5];
u8 log_max_eq_sz[0x8];
- u8 relaxed_ordering_write[0x1];
+ u8 mkc_order_write_after_write_ro[0x1];
u8 relaxed_ordering_read_pci_enabled[0x1];
u8 log_max_mkey[0x6];
u8 reserved_at_f0[0x6];
@@ -1951,7 +1951,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_320[0x3];
u8 log_max_transport_domain[0x5];
u8 reserved_at_328[0x2];
- u8 relaxed_ordering_read[0x1];
+ u8 pci_relaxed_ordered_read[0x1];
u8 log_max_pd[0x5];
u8 dp_ordering_ooo_all_ud[0x1];
u8 dp_ordering_ooo_all_uc[0x1];
@@ -4528,7 +4528,7 @@ struct mlx5_ifc_mkc_bits {
u8 reserved_at_2[0x1];
u8 access_mode_4_2[0x3];
u8 reserved_at_6[0x7];
- u8 relaxed_ordering_write[0x1];
+ u8 order_write_after_write[0x1];
u8 reserved_at_e[0x1];
u8 small_fence_on_rdma_read_response[0x1];
u8 umr_en[0x1];
@@ -4570,7 +4570,7 @@ struct mlx5_ifc_mkc_bits {
u8 translations_octword_size[0x20];
u8 reserved_at_1c0[0x19];
- u8 relaxed_ordering_read[0x1];
+ u8 pci_relaxed_ordered_read[0x1];
u8 log_page_size[0x6];
u8 reserved_at_1e0[0x5];
--
2.52.0
next prev parent reply other threads:[~2026-11-02 22:34 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-02 22:32 [PATCH rdma-next v2 00/15] RDMA: Support HW requiring relaxed ordering and add Unordered access flag Michael Gur
2026-11-02 22:32 ` [PATCH rdma-next v2 01/15] RDMA/mlx5: Allow optional access flags in DM registration Michael Gur
2026-11-03 22:34 ` sashiko-bot
2026-11-02 22:32 ` [PATCH rdma-next v2 02/15] RDMA/mlx5: Allow optional access flags in DEVX UMEM registration Michael Gur
2026-11-03 22:34 ` sashiko-bot
2026-11-02 22:32 ` [PATCH rdma-next v2 03/15] RDMA/core: Allow optional access flags in dmabuf reg ioctl Michael Gur
2026-11-03 22:34 ` sashiko-bot
2026-11-02 22:32 ` [PATCH rdma-next v2 04/15] RDMA/core: Allow optional access flags in reg mr ioctl Michael Gur
2026-11-03 22:34 ` sashiko-bot
2026-11-02 22:32 ` Michael Gur [this message]
2026-11-03 22:34 ` [PATCH rdma-next v2 05/15] mlx5: Rename IFC bits of relaxed ordering fields sashiko-bot
2026-11-02 22:32 ` [PATCH rdma-next v2 06/15] net/mlx5: Add IFC bits for new ordering caps Michael Gur
2026-11-03 22:34 ` sashiko-bot
2026-11-02 22:33 ` [PATCH rdma-next v2 07/15] mlx5: Consolidate mkey ordering setting into a single core helper Michael Gur
2026-11-03 22:34 ` sashiko-bot
2026-11-02 22:33 ` [PATCH rdma-next v2 08/15] net/mlx5: Enable relaxed ordering on resource dump mkey Michael Gur
2026-11-03 22:35 ` sashiko-bot
2026-11-02 22:33 ` [PATCH rdma-next v2 09/15] net/mlx5: Enable relaxed ordering on FW tracer mkey Michael Gur
2026-11-03 22:35 ` sashiko-bot
2026-11-02 22:33 ` [PATCH rdma-next v2 10/15] vfio/mlx5: Enable relaxed ordering on the live migration data mkey Michael Gur
2026-11-03 22:35 ` sashiko-bot
2026-11-02 22:33 ` [PATCH rdma-next v2 11/15] RDMA/mlx5: Enable relaxed ordering on ODP null mkey Michael Gur
2026-11-03 22:35 ` sashiko-bot
2026-11-02 22:33 ` [PATCH rdma-next v2 12/15] RDMA/mlx5: Converge UMR access-flag cap checks Michael Gur
2026-11-03 22:35 ` sashiko-bot
2026-11-02 22:33 ` [PATCH rdma-next v2 13/15] RDMA/uverbs: Add new Unordered MR access flag Michael Gur
2026-11-03 22:35 ` sashiko-bot
2026-11-02 22:33 ` [PATCH rdma-next v2 14/15] RDMA/mlx5: Support new Unordered " Michael Gur
2026-11-03 22:35 ` sashiko-bot
2026-11-05 14:50 ` Michael Gur
2026-11-02 22:33 ` [PATCH rdma-next v2 15/15] RDMA/mlx5: Enforce relaxed ordering when HW requires it Michael Gur
2026-11-03 22:35 ` sashiko-bot
2026-11-05 15:00 ` Michael Gur
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