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X-Spam-Score: -1.9 (-) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Chris Morgan Add the timer node for the rk356x. The timer is present at the SoC level and is register compatible with the rk3288 timer. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 1a4562df20ee..cc3faeb9a86d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1373,6 +1373,14 @@ i2c5: i2c@fe5e0000 { status = "disabled"; }; + timer0: timer@fe5f0000 { + compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfe5f0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + wdt: watchdog@fe600000 { compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; reg = <0x0 0xfe600000 0x0 0x100>; -- 2.53.0 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; 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Tue, 03 Nov 2026 07:31:49 -0800 (PST) Received: from neuromancer ([75.28.21.198]) by smtp.gmail.com with ESMTPSA id 5614622812f47-5640fd95dc0sm11599188b6e.6.2026.11.03.07.31.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 07:31:49 -0800 (PST) From: Chris Morgan To: linux-rockchip@lists.infradead.org Cc: devicetree@vger.kernel.org, shawn.lin@rock-chips.com, diederik@cknow-tech.com, michael.riesch@collabora.com, heiko@sntech.de, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org, Chris Morgan Subject: [PATCH 2/2] arm64: dts: rockchip: Add timer node for rk356x Date: Tue, 3 Nov 2026 09:31:44 -0600 Message-ID: <20261103153144.343764-3-macroalpha82@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261103153144.343764-1-macroalpha82@gmail.com> References: <20261103153144.343764-1-macroalpha82@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Chris Morgan Add the timer node for the rk356x. The timer is present at the SoC level and is register compatible with the rk3288 timer. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 1a4562df20ee..cc3faeb9a86d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1373,6 +1373,14 @@ i2c5: i2c@fe5e0000 { status = "disabled"; }; + timer0: timer@fe5f0000 { + compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfe5f0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + wdt: watchdog@fe600000 { compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; reg = <0x0 0xfe600000 0x0 0x100>; -- 2.53.0