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Tue, 03 Nov 2026 11:05:42 -0800 (PST) Received: from i4-gl-tmk5904.ad.psu.edu ([130.203.156.186]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-54b100ab8e4sm3527701cf.7.2026.11.03.11.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 11:05:41 -0800 (PST) From: Yuho Choi To: Jerome Forissier Cc: Tom Rini , Patrice Chotard , Michael Chang , Stanley Chu , Sean Anderson , Simon Glass , u-boot@lists.u-boot-project.org, Yuho Choi Subject: [PATCH] net: designware: Release the clocks if the PHY supply fails Date: Tue, 3 Nov 2026 14:05:21 -0500 Message-ID: <20261103190537.1096121-1-oss.patchbox@gmail.com> X-Mailer: git-send-email 2.43.0 X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 03 Nov 2026 20:53:47 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 designware_eth_probe() enables the clocks of the MAC before it enables the PHY supply. If regulator_set_enable_if_allowed() fails, or on NPCM8xx if setting "phy-supply-microvolt" fails, the probe returns directly and skips the clk_release_all() at the end of the function. A failed probe does not call designware_eth_remove(), so the clocks are left enabled. Go to the error path instead, as the later failures in the probe do. This uses the mdio_err label, because clk_err only exists with CONFIG_CLK; nothing between the two labels has been set up yet. The PHY supply itself is still left enabled, as on the other error paths and in designware_eth_remove(). Fixes: ba1f96672522 ("net: designware: add clock support") Fixes: 8897f91a5397 ("net: designware: support phy io micro voltage setting.") Signed-off-by: Yuho Choi --- Build-tested only, on nanopi-r2s-rk3328 and A20-OLinuXino-Lime2 (CLK=y, DM_REGULATOR=y), arbel_evb (NPCM8XX) and socfpga_arria10 (DM_REGULATOR=n), with no new warnings in designware.c at W=1. I also compiled designware.c with CONFIG_CLK undefined, since CLK is selected on all these boards. Not tested at runtime: I have no board where the PHY supply fails. drivers/net/designware.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 9470804ebd1..52dd08da82a 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -927,7 +927,8 @@ int designware_eth_probe(struct udevice *dev) ret = regulator_set_enable_if_allowed(phy_supply, true); if (ret) { puts("Error enabling phy supply\n"); - return ret; + err = ret; + goto mdio_err; } #if IS_ENABLED(CONFIG_ARCH_NPCM8XX) int phy_uv; @@ -937,7 +938,8 @@ int designware_eth_probe(struct udevice *dev) ret = regulator_set_value(phy_supply, phy_uv); if (ret) { puts("Error setting phy voltage\n"); - return ret; + err = ret; + goto mdio_err; } } #endif -- 2.43.0