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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48fea18104bsm467832f8f.6.2026.11.03.14.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 14:38:48 -0800 (PST) Date: Tue, 3 Nov 2026 22:38:46 +0000 From: David Laight To: Demian Shulhan Cc: saeed bishara , Catalin Marinas , Will Deacon , Mark Rutland , Eric Biggers , Andrew Morton , Marco Elver , Ard Biesheuvel , Robin Murphy , David Gow , Brendan Higgins , Nathan Chancellor , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kunit-dev@googlegroups.com, netdev@vger.kernel.org, llvm@lists.linux.dev Subject: Re: [PATCH 0/2] arm64: csum: Add fused copy and Internet checksum Message-ID: <20261103223846.5e6a1dfc@pumpkin> In-Reply-To: References: <20260927131838.6774-1-demyansh@gmail.com> <20260927184414.6c0c8867@pumpkin> <20261102161426.2403d308@pumpkin> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) X-Mailing-List: llvm@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Tue, 3 Nov 2026 16:47:29 +0100 Demian Shulhan wrote: > > .L4: > > ldr x1, [x0, x4] > > adds x2, x2, x1 > > cinc x3, x3, cs # adc $0,%rxx on x86 > > adds x4, x4, 8 > > bne .L4 =20 > Agreed, that is a nice loop for the sum-only case, one dependent op on > the sum chain and no builtin needed. > For the copy case I tried the same form on x86 (Zen 3, GCC 15, Clang > 19-22, -O2) with a store added, against csum-copy_64.S, as posted it ran > at 0.85x of the asm with GCC and 0.73-0.76x with Clang (which rewrites > it into setb/adc), and ~0.8x unrolled 2x/4x - a bit slower than the > posted 4-accumulator loop (0.88-0.95x). I just added *(u64 *)(dest + count) =3D val to one of my loops. gcc just replaces the 'add from memory' with mov/mov/add. I'm now confused though, I seem to be getting different output from earlier. With -Os (which I didn't think I was passing) clang is refusing to do the 'offset from end of buffer' loop. With -O2 it bloats everything by unrolling 4 times and adding lots of extra instructions. (AFAICT the optimiser has a completely incorrect cpu model.) If the compiler doesn't generate the expected code it is all pointless. The xor parity code loop had to be in the asm block to stop the compiler changing it to a much slower form. For the checksum code I have managed to work out how many bytes/clock the code was generating and getting it to (reasonably) match the expected values. But you have to use relatively short buffers to avoid D-cache effects. David >=20 > =D0=BF=D0=BD, 2 =D0=BB=D0=B8=D1=81=D1=82. 2026=E2=80=AF=D1=80. =D0=BE 17:= 14 David Laight =D0=BF=D0=B8=D1=88=D0=B5: >=20 >=20 > > > > On Mon, 2 Nov 2026 16:14:06 +0100 > > Demian Shulhan wrote: > > =20 > > > > The scalar path seems like generic C code and not restricted to arm= 64, > > > > curious how that performs against existing (e.g. x86) assembly > > > > optimized implementation. =20 > > > Depends. I think __builtin_addcll() is needed to get roughly the same > > > performance as the asm version. In my tests GCC on arm64 turns it > > > into adds + cset instead of adcs like on x86. > > > But I will look at it, thanks! =20 > > > > The C version I posted earlier has the loop: > > buf +=3D count; > > count =3D -count; > > sum =3D carry =3D 0; > > do { > > val =3D *(u64 *)(buf + count); > > sum +=3D val; > > carry +=3D sum < val; > > } while ((count +=3D 8)); > > > > for aarch64 you get: > > .L4: > > ldr x1, [x0, x4] > > adds x2, x2, x1 > > cinc x3, x3, cs # adc $0,%rxx on x86 > > adds x4, x4, 8 > > bne .L4 > > > > I suspect that is close to optimal - especially for fast cpu with > > out of order execution. > > > > https://godbolt.org/z/eso79K7Wq > > > > David > > =20 > > > > > > =D0=BF=D0=BD, 2 =D0=BB=D0=B8=D1=81=D1=82. 2026=E2=80=AF=D1=80. =D0=BE= 12:44 saeed bishara =D0=BF=D0=B8=D1=88=D0=B5:= =20 > > > > > > > > On Sun, Nov 1, 2026 at 3:34=E2=80=AFPM Demian Shulhan wrote: =20 > > > > > > > > > > I would prefer to keep only the scalar version of the fused copy+= csum. > > > > > It reads the data once instead of twice, and on real Armv9 hardwa= re it > > > > > cuts end-to-end cycles/byte for bulk TCP over WireGuard by 3-12% > > > > > depending on the core (+6-8% throughput). It uses only general-pu= rpose > > > > > registers, so there is no FPSIMD state to save and it is safe in = any > > > > > context. > > > > > > > > > > If you are OK with the scalar path, I can send v2 with NEON dropp= ed, > > > > > the scalar path only, and the KUnit fix for the x86 zero-length c= ase > > > > > Jakub reported. > > > > > =20 > > > > The scalar path seems like generic C code and not restricted to arm= 64, > > > > curious how that performs against existing (e.g. x86) assembly > > > > optimized implementation. > > > > saeed =20 > > =20