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[144.49.247.13]) by smtp-relay.gmail.com with ESMTPS id 00721157ae682-8b309d400c1sm180897b3.27.2026.11.04.04.10.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Nov 2026 04:10:58 -0800 (PST) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-dl1-f71.google.com with SMTP id a92af1059eb24-147be78cd56so524829c88.1 for ; Wed, 04 Nov 2026 04:10:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1793794257; x=1794399057; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Q6d7mX52ZIS3nYrkqsRL0QIyJ6xOO1u5oHUZ/QcUNHM=; b=B0RQplVmSLuXk3fqgw++DUXQpFCjqyepiqv4C6B4VRNbPWFxBHzJUp56s5UDt7FYoA OPU1lAcuvxMe/MwqQkkSV26A4ViX8/+on0wfSfQ9f00Sz4SDsS/TFgBa0+9SEuk/IQh7 AtmMOCwdDGOlq1KxjWcad4BGNyka5a9rhoPfg= X-Received: by 2002:a05:7022:3b88:b0:16d:1e24:5cc3 with SMTP id a92af1059eb24-1ac5c64c610mr26813545c88.19.1793794256619; Wed, 04 Nov 2026 04:10:56 -0800 (PST) X-Received: by 2002:a05:7022:3b88:b0:16d:1e24:5cc3 with SMTP id a92af1059eb24-1ac5c64c610mr26813480c88.19.1793794255169; Wed, 04 Nov 2026 04:10:55 -0800 (PST) Received: from localhost.localdomain ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b245c6f0dcsm9377095c88.21.2026.11.04.04.10.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 04:10:54 -0800 (PST) From: Ranjan Kumar To: linux-scsi@vger.kernel.org, martin.petersen@oracle.com Cc: sathya.prakash@broadcom.com, chandrakanth.patil@broadcom.com, sweeti.vandure@broadcom.com, vishakhavc@google.com, ipylypiv@google.com, Ranjan Kumar , Sashiko Subject: [PATCH 19/21] scsi: mpi3mr: Fix byte order handling in the NVMe passthrough commands Date: Wed, 4 Nov 2026 17:31:00 +0530 Message-ID: <20261104120103.503871-20-ranjan.kumar@broadcom.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261104120103.503871-1-ranjan.kumar@broadcom.com> References: <20261104120103.503871-1-ranjan.kumar@broadcom.com> X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e The NVMe passthrough code reads the command dword that selects PRP or SGL and applies the SGE modifier to the addresses without converting between CPU and little endian byte order. On a big endian host the wrong data format is chosen and the modifier bits end up in the wrong place of the address. Convert the command dword when reading it, and keep the modifier mask and value in little endian form like the address fields they are applied to. Fixes: 7dbd0dd8cde3 ("scsi: mpi3mr: Add support for NVMe passthrough") Reported-by: Sashiko Closes: https://sashiko.dev/#/patchset/20260825210411.301535-1-chandrakanth.patil@broadcom.com?part=2 Signed-off-by: Ranjan Kumar --- drivers/scsi/mpi3mr/mpi3mr_app.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/scsi/mpi3mr/mpi3mr_app.c b/drivers/scsi/mpi3mr/mpi3mr_app.c index 310ead2c644e..2dc6fad7a37b 100644 --- a/drivers/scsi/mpi3mr/mpi3mr_app.c +++ b/drivers/scsi/mpi3mr/mpi3mr_app.c @@ -1969,7 +1969,7 @@ static unsigned int mpi3mr_get_nvme_data_fmt( { u8 format = 0; - format = ((nvme_encap_request->command[0] & 0xc000) >> 14); + format = ((le32_to_cpu(nvme_encap_request->command[0]) & 0xc000) >> 14); return format; } @@ -1998,10 +1998,10 @@ static int mpi3mr_build_nvme_sgl(struct mpi3mr_ioc *mrioc, u16 available_sges = 0, i; u32 sge_element_size = sizeof(struct mpi3mr_nvme_pt_sge); struct mpi3mr_buf_map *drv_buf_iter = drv_bufs; - u64 sgemod_mask = ((u64)((mrioc->facts.sge_mod_mask) << - mrioc->facts.sge_mod_shift) << 32); - u64 sgemod_val = ((u64)(mrioc->facts.sge_mod_value) << - mrioc->facts.sge_mod_shift) << 32; + __le64 sgemod_mask = cpu_to_le64(((u64)((mrioc->facts.sge_mod_mask) << + mrioc->facts.sge_mod_shift) << 32)); + __le64 sgemod_val = cpu_to_le64(((u64)(mrioc->facts.sge_mod_value) << + mrioc->facts.sge_mod_shift) << 32); u32 size; nvme_sgl = (struct mpi3mr_nvme_pt_sge *) @@ -2097,10 +2097,10 @@ static int mpi3mr_build_nvme_prp(struct mpi3mr_ioc *mrioc, size_t length = 0, desc_len; u8 count; struct mpi3mr_buf_map *drv_buf_iter = drv_bufs; - u64 sgemod_mask = ((u64)((mrioc->facts.sge_mod_mask) << - mrioc->facts.sge_mod_shift) << 32); - u64 sgemod_val = ((u64)(mrioc->facts.sge_mod_value) << - mrioc->facts.sge_mod_shift) << 32; + __le64 sgemod_mask = cpu_to_le64(((u64)((mrioc->facts.sge_mod_mask) << + mrioc->facts.sge_mod_shift) << 32)); + __le64 sgemod_val = cpu_to_le64(((u64)(mrioc->facts.sge_mod_value) << + mrioc->facts.sge_mod_shift) << 32); u16 dev_handle = le16_to_cpu(nvme_encap_request->dev_handle); struct mpi3mr_tgt_dev *tgtdev; u16 desc_count = 0; -- 2.47.3