From: Junjie Cao <junjie.cao@linux.dev>
To: shrihari.s@samsung.com
Cc: jic23@kernel.org, linux-cxl@vger.kernel.org,
linux-pci@vger.kernel.org, qemu-devel@nongnu.org,
anisa.su887@gmail.com, mst@redhat.com,
marcel.apfelbaum@gmail.com, arun.george@samsung.com,
cpgs@samsung.com, dave@stgolabs.net, dongjoo.seo1@samsung.com,
gost.dev@samsung.com, s.neeraj@samsung.com,
vikash.k5@samsung.com, anisa.su@samsung.com,
junjie.cao@linux.dev
Subject: Re: [PATCH qemu v1 7/8] hw/cxl: Wire SVC and Dev3 capabilities to CXL Type 3 device
Date: Wed, 4 Nov 2026 11:25:27 -0600 [thread overview]
Message-ID: <20261104172527.2172366-4-junjie.cao@linux.dev> (raw)
In-Reply-To: <331418503.141793792283935.JavaMail.epsvc@epcpadp2new>
Tested Type-3 capability enumeration and UIO/SVC/flit dependency
combinations at cold boot and after system reset on q35, with the
full series on 3c99db7705c1.
Linux UIO discovery and a 1-way UIO region commit also passed with
Davidlohr's pcie-uio-rfc kernel [1]. For that kernel's UIO checks,
QEMU used hdm-db=on and CFMWS restrictions=0x2d; the guest kernel
enabled CONFIG_CXL_REGION_INVALIDATION_TEST to allow region setup
in the VM.
[1] https://github.com/davidlohr/linux/commit/4726547f45a612b2d953f5f4e13ab6fe34672c7c
Tested-by: Junjie Cao <junjie.cao@linux.dev>
next prev parent reply other threads:[~2026-11-04 17:25 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20261104113014epcas5p1dbf4b09e2849d28b46eb39db7990a54f@epcas5p1.samsung.com>
[not found] ` <20261104115242.2035807-1-shrihari.s@samsung.com>
2026-11-04 11:52 ` [PATCH qemu v1 1/8] hw/pci: Refactor flitmode from PCIESlot to PCIEPort Shrihari E S
2026-11-04 11:52 ` [PATCH qemu v1 2/8] hw/pci: Move 'x-256b-flit' property from cxl_root_port to pcie_root_port Shrihari E S
2026-11-04 11:52 ` [PATCH qemu v1 3/8] hw/cxl: Wire UIO capability into HDM decoder and DVSEC registers Shrihari E S
2026-11-04 17:25 ` Junjie Cao
2026-11-04 11:52 ` [PATCH qemu v1 4/8] hw/pci: Add PCIe Streamlined Virtual Channel (SVC) capability Shrihari E S
2026-11-04 17:25 ` Junjie Cao
2026-11-04 11:52 ` [PATCH qemu v1 5/8] hw/pci: Wire SVC initialization into port realize functions Shrihari E S
2026-11-04 17:25 ` Junjie Cao
2026-11-04 11:52 ` [PATCH qemu v1 6/8] hw/pci: Add PCIe Device3 capability support Shrihari E S
2026-11-04 11:52 ` [PATCH qemu v1 7/8] hw/cxl: Wire SVC and Dev3 capabilities to CXL Type 3 device Shrihari E S
2026-11-04 17:25 ` Junjie Cao [this message]
2026-11-04 11:52 ` [PATCH qemu v1 8/8] cxl: Add documentation for CXL UIO support Shrihari E S
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