Re: [PATCH RFC 0/7] QEMU/hw/cxl: Allow CXL Type 3 memory regions to be initialized at guest boot

[Jonathan Cameron <jic23@kernel.org>]

On Mon, 26 Oct 2026 19:03:21 +0900
Yukiya Takaki <fj2110jc@fujitsu.com> wrote:

> Hello everyone,
> 
> I’m a student intern, and this is my first time sending patches to an open source mailing list.
> 
> This patch series configures QEMU’s CXL Type 3 devices so that guest operating systems can automatically discover
> and create CXL regions during boot, aligning QEMU’s behavior with real hardware.

Hi Yukiya,

Interesting project.

> 
> Background and motivation
>   Currently, during guest boot QEMU does not provide the information or register programming needed for the guest OS
>   to initialize CXL Type 3 memory, so using it still requires an explicit action in the guest (for example, running the cxl create-region command).
>   By contrast, on some physical systems the firmware automatically allocates CXL memory ranges and exposes them to the OS,
>    allowing the Linux CXL driver to discover and create regions during boot.
>   This patch series is a first, experimental attempt to reproduce that behavior in QEMU.
> 
>   Some parts of this implementation are based on Li, Zhijian’s work in:
>   https://github.com/zhijianli88/qemu/tree/program-decoder-v2
> 
>   I would like to ask for feedback on whether this approach makes sense and whether I should continue to enhance it.
> 
> Approach
>   This patch first adds a program_hdm_decoder option to cxl-type3.
>   When program-hdm-decoder is enabled on cxl-type3, QEMU will:
>     1) program endpoint/host-bridge HDM decoder state,
>     2) expose Type 3 ranges as E820_SOFT_RESERVED on x86,
>     3) create memory-only NUMA nodes for those ranges,
>     4) emit SRAT memory-affinity entries mapping each Type 3 HPA range to its node ID
> 
>   On real hardware, HDM decoder programming and memory layout are typically handled by firmware, so they would ideally be managed by SeaBIOS.
>   However, in the current QEMU/SeaBIOS model, E820 and SRAT are built on the QEMU side, and pushing HDM decoder programming
>   into SeaBIOS would introduce additional complexity and risk inconsistencies.

So, did you explore doing this in a similar fashion to PCI enumeration?

That's done the bios and is very similar in that there is a mix of
policy and rules in how it is configured that we really don't want
in qemu.  With that ACPI tables are then built in QEMU that contain
values read back from what was setup. The main thing I'm thinking of
here is the PXB handling that relies on the bios having done the
PCI enumeration first rather than doing it in qemu.
The arm code is here
https://elixir.bootlin.com/qemu/v11.1.3/source/hw/pci-host/gpex-acpi.c#L103
x86 probably this:
https://elixir.bootlin.com/qemu/v11.1.3/source/hw/i386/acpi-build.c#L1038

My immediate instinct is that would look more like a conventional bios
flow.  It would also have the significant benefit of putting the enumerating
and configuration code into an open source bios, something I hoped would come out
early ARM work on this (see linux plumbers - I think this is right session)
https://lpc.events/event/16/contributions/1254/attachments/1113/2136/CXL%20Type-3%20device%20discovery,%20configuration%20in%20firmware%20and%20prepare%20ACPI%20tables%20for%20kernel%20usage.pdf

Then we'd regenerate the SRAT, HMAT etc before handling to the OS.
(I'm not sure this works for e820 having never touched that flow).

There is a lot of policy involved in CXL configuration and I'd not
want to replicate that part in QEMU. At best we'd want to pass
some hints to the bios.

Flow wise that would mean adding to acpi_build_update() some code
to do the necessary srat and other table updates.  That would
definitely work for the actual ACPI tables, but I gather e820 is
rather different...  However, e820 real table is I think
actually constructed by seabios so can that just make the
necessary updates after programming the CXL decoders etc?

Now if you did this on SBSA-ref and arm you'd have to do it
all in the bios (as that generates everything) and the whole
problem would be much more standard.

Given we have that option on arm/sbsa-ref I don't currently
see a reason to explore the bios flows on arm/virt.

I also gather (from asking an LLM so might be wrong) that there
are options that boot qemu on x86 with tables generated
by the bios, not qemu.  Legacy path in seabios, coreboot and
and ovmf path used with xen.  Maybe working with them avoids
the extra complexity of bounce backwards and forwards between
qemu and the firmware (though I think I'd probably avoid these).

Anyhow, interested to see where you go with this.
Definitely useful for those of us working with platforms that
never do the bios programmed flow but have to test it when
making changes!

Jonathan

> 
> Testing
>   We ran tests in the following environment and confirmed that CXL regions were created at boot, NUMA nodes were set up,
>   and E820_SOFT_RESERVED entries appeared in the E820 table:
> 
>   - BIOS: SeaBIOS c2a33ad9ad1452e23b41c4ac44a3bc6be8ebc4cf
>   - CXL memory: 4 GB
>   - CFMWS: 4 GB
>   - Host bridge: 1
> 
>   The following is the startup script.
> 
>   sudo /path/to/qemu/build/qemu-system-x86_64 \
>     -name guest=cxl \
>     -nographic \
>     -machine q35,accel=tcg,nvdimm=on,cxl=on \
>     -cpu max -smp 4,sockets=4,cores=1,threads=1 \
>     -m size=4G,slots=10,maxmem=20G \
>     -drive file=/path/to/image.qcow2,format=qcow2,index=0,media=disk,id=hd \
>     -bios /path/to/seabios/out/bios.bin \
>     -nic bridge,br=virbr0,model=e1000e,mac=52:54:00:b5:4e:7c \
>     -object memory-backend-ram,size=2G,id=m0 \
>     -object memory-backend-ram,size=2G,id=m1 \
>     -numa node,nodeid=0,cpus=0-1,memdev=m0 \
>     -numa node,nodeid=1,cpus=2-3,memdev=m1 \
>     -device pcie-root-port,id=pci-root,slot=4,bus=pcie.0,chassis=0 \
>     -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1,hdm_for_passthrough=true \
>     -device cxl-rp,port=0,id=root_port13,bus=cxl.1,chassis=0,slot=2 \
>     -object memory-backend-ram,size=4G,share=on,id=vmem0 \
>     -device cxl-type3,bus=root_port13,volatile-memdev=vmem0,id=cxl-vmem0,program-hdm-decoder=true \
>     -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k
>   
>   Furthermore, we conducted the experiment in which we added two CXL Type3.
> 
>   - CXL memory: 4 GB × 2
>   - CFMWS: 4 GB × 2
> 
>   The following is the startup script.
>     
>   sudo /path/to/qemu/build/qemu-system-x86_64 \
>     -name guest=cxl \
>     -nographic \
>     -machine q35,accel=tcg,nvdimm=on,cxl=on,hmat=on \
>     -cpu max -smp 4,sockets=4,cores=1,threads=1 \
>     -m size=4G,slots=10,maxmem=20G \
>     -drive file=/path/to/image.qcow2,format=qcow2,index=0,media=disk,id=hd \
>     -bios /path/to/seabios/out/bios.bin \
>     -nic bridge,br=virbr0,model=e1000e,mac=52:54:00:b5:4e:7c \
>     -object memory-backend-ram,size=2G,id=m0 \
>     -object memory-backend-ram,size=2G,id=m1 \
>     -numa node,nodeid=0,cpus=0-1,memdev=m0 \
>     -numa node,nodeid=1,cpus=2-3,memdev=m1 \
>     -device pcie-root-port,id=pci-root,slot=4,bus=pcie.0,chassis=0 \
>     -device pcie-root-port,id=pci-root-net,chassis=5,slot=5,bus=pcie.0 \
>     -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1,hdm_for_passthrough=true \
>     -device cxl-rp,port=0,id=root_port13,bus=cxl.1,chassis=0,slot=2 \
>     -device cxl-rp,port=3,id=root_port14,bus=cxl.1,chassis=2,slot=4 \
>     -object memory-backend-ram,size=4G,share=on,id=vmem0 \
>     -object memory-backend-ram,size=4G,share=on,id=vmem1 \
>     -device cxl-type3,bus=root_port13,volatile-memdev=vmem0,id=cxl-vmem0,program-hdm-decoder=true \
>     -device cxl-type3,bus=root_port14,volatile-memdev=vmem1,id=cxl-vmem1,program-hdm-decoder=true \
>     -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k,cxl-fmw.1.targets.0=cxl.1,cxl-fmw.1.size=4G,cxl-fmw.1.interleave-granularity=4k
> 
> 
> How to use
>   Specify the following parameters when starting QEMU:
> 
>   - bios <SeaBIOS binary that includes commit c2a33ad9ad1452e23b41c4ac44a3bc6be8ebc4cf> to ensure that E820_SOFT_RESERVED entries are exposed
>   - Add hmat=on to the -machine option [1]
>   - Add program-hdm-decoder=true to each -device cxl-type3 option
>     [1] On Linux, the kernel first checks E820_SOFT_RESERVED ranges. When multiple CXL Type 3 devices share a contiguous HPA range,
>         these ranges tend to be merged into a single region, so the CXL driver cannot reliably initialize per‑device regions based on E820 alone.
>         SRAT entries for CXL memory are therefore needed, and the guest seems to discard SRAT when `hmat=on` is not specified,
>         so HMAT must be enabled.
> 
> QEMU base commit: bddb785e791e415db38884848d068457e226f5e3
> 
> TODO
>   With the current implementation of this patch, the following configurations are either not supported or have not been sufficiently tested.
>   As a result, automatic creation of CXL regions in the guest OS may fail:
> 
>   - A CXL persistent memory device is included
>   - Interleaved configurations
>   - Cases where the memory size specified by CFMWS does not match the size of the CXL Type 3 backend memory
>   - Configurations where CXL memory is attached via a switch
>   - Multi-target CFMWS environments
>   - ARM environments
>   - HMAT does not yet include information about CXL memory devices
> 
>   The following behaviors are also provisional implementations and may need further refinement:
>    - A new NUMA node ID is assigned to each CXL memory device. This should be improved either to reflect more accurate NUMA distances for CXL memory,
>      or to allow the NUMA node IDs to be specified by the user.
>    - Assignment of CXL Type 3 devices to CFMWS address ranges. On physical systems, platform firmware typically generates CFMWS entries
>      based on the detected CXL topology and its address-space allocation. In QEMU, however, CFMWS entries are configured explicitly
>      through machine options. The current implementation therefore has to infer which CFMWS range should be used for each Type 3 device.
>      This selection logic may need further refinement. Possible approaches include improving the selection and validation logic,
>      adding an explicit option to associate each Type 3 device with a CFMWS entry,
>      or generating CFMWS entries automatically from the configured CXL topology and devices.
>    - HDM decoder reset sequencing and state reconstruction.
>      The current implementation prevents the host bridge HDM decoder configuration from being overwritten later in the same reset
>      by moving the common initialization of the host bridge component registers from the reset path to the realization path.
>      However, ideally, after the registers have been restored to their reset values, the host bridge HDM decoder configuration
>      automatically programmed by QEMU should be reconstructed as part of reset processing.
> 
> Thanks,
> 
> ------
> 
> Yukiya Takaki (7):
>   QEMU/hw/cxl: add program-hdm-decoder option for CXL Type 3 devices
>   QEMU/hw/cxl:add HPA offset tracking for CXL Type 3 devices
>   QEMU: hw/cxl: add helper to get HPA range for CXL Type 3
>   QEMU/hw/cxl: auto‑program HDM decoders for CXL Type 3
>   QEMU/hw/cxl: expose CXL Type 3 ranges as E820_SOFT_RESERVED on x86
>   QEMU/hw/cxl: Create NUMA nodes for CXL Type 3 memory
>   add CXL Type 3 memory ranges to SRAT
> 
>  hw/acpi/cxl_type3.c                 |  30 +++++
>  hw/acpi/meson.build                 |   1 +
>  hw/arm/cxl.c                        |  10 ++
>  hw/arm/meson.build                  |   2 +
>  hw/cxl/cxl-host.c                   |  63 ++++++++++
>  hw/i386/acpi-build.c                |   7 ++
>  hw/i386/cxl.c                       |  11 ++
>  hw/i386/meson.build                 |   1 +
>  hw/i386/pc.c                        |   2 +
>  hw/mem/cxl_type3.c                  | 177 ++++++++++++++++++++++++++++
>  hw/pci-bridge/pci_expander_bridge.c |  13 +-
>  include/hw/cxl/cxl.h                |   2 +
>  include/hw/cxl/cxl_device.h         |   6 +
>  include/hw/cxl/cxl_host.h           |   3 +
>  include/hw/mem/cxl_type3.h          |   8 ++
>  15 files changed, 334 insertions(+), 2 deletions(-)
>  create mode 100644 hw/acpi/cxl_type3.c
>  create mode 100644 hw/arm/cxl.c
>  create mode 100644 hw/i386/cxl.c
>  create mode 100644 include/hw/mem/cxl_type3.h
>