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Thu, 05 Nov 2026 16:09:02 -0800 (PST) Received: from X870E-AORUS-MASTER.kkp-group.com ([2400:4053:d960:1a00:d4e5:611a:d757:e515]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36fa922b205sm663887eec.11.2026.11.05.16.09.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 16:09:02 -0800 (PST) From: Shigeaki Asai To: FUKAUMI Naoki , Kever Yang , Quentin Schulz Cc: Jonas Karlman , Simon Glass , Tom Rini , Ilias Apalodimas , u-boot@lists.u-boot-project.org, Shigeaki Asai Subject: [PATCH] rockchip: rock-4c-plus: Configure IO domains in SPL Date: Fri, 6 Nov 2026 09:08:15 +0900 Message-ID: <20261106000815.217889-1-asai.6265@gmail.com> X-Mailer: git-send-email 2.43.0 X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Fri, 06 Nov 2026 04:44:59 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Shigeaki Asai On the ROCK 4C+, nothing is printed on the debug UART after a cold boot until U-Boot proper configures the regulators, so the TPL and SPL output is lost. The IO domains of UART2 (APIO4) and PMUIO2 are supplied by vcc_3v0_s0, which is LDO7 of the RK809. This LDO comes up at 1.8V at power-on (measured on the UART TX pin). U-Boot proper later sets it to 3.0V and configures the IO domains to match. Enable the PMIC, regulator and IO domain drivers in SPL, and add bootph-pre-ram to the related nodes. The IO domain driver then sets vcc_3v0_s0 to 3.0V and configures the IO domains early in SPL. With this, the output is visible from SPL on a cold boot. The TPL output is still not visible. Tested on ROCK 4C+ V1.41. This patch was written with the help of Claude (claude-opus-5-5). Signed-off-by: Shigeaki Asai --- Tested on top of the series "ram: rk3399: Fix LPDDR4 tRFCab for high-density devices", because this board does not boot without it: https://lore.kernel.org/all/20261101185441.755448-1-asai.6265@gmail.com/ arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 32 ++++++++++++++++++++ configs/rock-4c-plus-rk3399_defconfig | 7 +++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi index 7a6af430a6f..6094cda551a 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -49,3 +49,35 @@ &vdd_log { regulator-init-microvolt = <950000>; }; + +&i2c0 { + bootph-pre-ram; +}; + +&i2c0_xfer { + bootph-pre-ram; +}; + +&pcfg_pull_none { + bootph-pre-ram; +}; + +&rk809 { + bootph-pre-ram; + + regulators { + bootph-pre-ram; + }; +}; + +&vcc_3v0_s0 { + bootph-pre-ram; +}; + +&io_domains { + bootph-pre-ram; +}; + +&pmu_io_domains { + bootph-pre-ram; +}; diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 0f6bdfdfb06..d3870586cf7 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock-4c-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SF_DEFAULT_BUS=1 @@ -24,6 +25,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -48,6 +51,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_SPL_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y @@ -65,7 +69,10 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_RK8XX=y +CONFIG_SPL_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 -- 2.43.0