Re: [PATCH 00/10] riscv: sun20i: add support for the Allwinner D1/D1s(F133) SoCs and boards

[Andre Przywara <andre.przywara@arm.com>]

On Sun,  1 Nov 2026 23:04:39 +0200
Indrek Kruusa <indrek.kruusa@gmail.com> wrote:

Hi Indrek,

thanks for sending this out.
This looks surprisingly simple on a first glance.
I haven't had a detailed look, but wanted to reply with some general
thoughts.

> Building upon the work of Samuel Holland [1], this series introduces support

I guess you took quite some patches from Samuel? I don't see him being
the author of any patch, that doesn't sound likely. Please try to
attribute his work, by keeping this authorship.

> for the Allwinner D1/D1s(F133) RISC-V SoCs and two development boards:
> 
> - Sipeed Lichee RV Dock (D1 SoC)
> - MangoPi MQ (RISC-V version with D1s/F133-A SoC)
> 
> The main difference from Samuel's work is how the boards are wired into the

I think Samuel also used DM_SPL (which I heavily oppose), looks like
this is gone as well? I like that, but it seems to be a major
difference worth mentioning.

> tree. The original design aimed at one cross-architecture configuration which
> covers ARM sun8i and RISC-V sun20i parts from Allwinner. This series does not
> do that. The D1/D1s get their own configuration instead:
> 
>   - arch/riscv/cpu/sun20i/ and board/sun20i/ hold the RISC-V side
>   - SUN20I is a SoC-family symbol, TARGET_SUN20I the board target
>   - the shared sunxi drivers accept SUN20I next to ARCH_SUNXI, so they are
>     shared as before -- only the Kconfig condition changes
> 
> Keeping the two sides apart has a cost: a few things exist twice.

Mmmh, I need to have a closer look, but am wondering if we can avoid
those double definitions and integrate both architectures better.
arch/arm vs. arm/riscv should separate itself naturally, and the
drivers shouldn't care about the architecture.
That's just a hunch, though, I will have a closer look in the next
weeks, as I am busy with other things.

Thanks,
Andre

> SUNXI_GEN_NCAT2 is declared in both arch trees, because the shared drivers
> test it and no Kconfig file is sourced by both. clock_get_pll6() is a C
> function for ARM (clock_sun50i_h6.c) and an inline for RISC-V
> (arch-sun20i/clock.h), decoding the same NCAT2 registers. The MMC mod-clock
> bits, the CCU offsets and parts of board/sunxi/board.c are repeated the same
> way.
> 
> For the sake of simplicity the image names stay "sunxi"
> (u-boot-sunxi-with-spl.bin, inner sunxi-spl.bin) because that is the shared
> Allwinner eGON boot format.
> 
> Both defconfigs build, and both boards boot from the SD card to a userspace
> login. The images were built with custom Buildroot configuration, using
> gcc 16.2.0, binutils 2.46.1 and Linux 7.3.0.
> 
> One caveat -- reboot does not work yet; it needs fixes outside U-Boot, on the
> firmware/OS side.
> 
> AI/LLM tools were used as development assistants throughout this work.
> Their use included debugging DRAM initialization and probing issues,
> assisting with code development, reviewing code, helping with testing and
> validation, and reviewing and refining commit messages.
> 
> PS. The boards use CONFIG_NS16550_CLK_ENABLE, which comes from a patch
> originally posted by khaliforce <kforce@gmail.com> and merged as commit
> 70f51e1e2ea5 ("serial: ns16550: make probe clock enabling optional") by
> Samuel Holland; v2027.01-rc1 already contains it.
> 
> [1] https://github.com/smaeul/u-boot/tree/d1-wip
> 
> 
> The patches (on tag v2027.01-rc1)
> ---------------------------------
> 
> 1/10 riscv: cpu: add Allwinner D1/D1s(F133) CPU support
>      Add the C906 support for the D1/D1s(F133) SoCs:
> 
>      - T-Head cache operations from the custom cache instructions
>      - harts_early_init() programming MXSTATUS, MHCR and MHINT
>      - cleanup_before_linux() disabling interrupts and flushing the caches
>      - dram_init() from the device tree memory nodes
>      - the T-Head CSR, CCU clock and memory map headers
>      - SUN20I Kconfig (cache line size, T-Head CMO support)
> 
> 2/10 sunxi: allow the sunxi drivers to be built for sun20i
>      Accept SUN20I next to ARCH_SUNXI for the RAM, clock, pinctrl, GPIO, MMC,
>      reset and watchdog drivers, and keep WATCHDOG_AUTOSTART off for it.
> 
>      Declare SUNXI_GEN_NCAT2 here as well - the ARM sunxi Kconfig is not read
>      by a RISC-V build - and add the MMC base addresses to arch-sun20i/cpu.h
>      so sunxi_mmc.c builds.
> 
> 3/10 board: sun20i: add common support for the D1/D1s boards
>      Add the board code used by all D1/D1s(F133) boards:
> 
>      - TARGET_SUN20I, board init and CPU probing
>      - sunxi eGON/TOC0 SPL header: boot source, FEL mode, SPL size
>      - SPL DRAM probing and the /memory fixup
>      - FIT DT name matching
>      - environment placement for MMC/SPI boot media
>      - the u-boot-sunxi-with-spl.bin image
>      - a MAINTAINERS section for the new board and CPU files
> 
>      CONFIG_ARCH_SUNXI is never set on these RISC-V parts, so extend the SPL
>      image rule in scripts/Makefile.xpl to match TARGET_SUN20I as well.
> 
>      The board code, the devicetree overlay and include/configs/sun20i.h come
>      from Samuel Holland's d1-wip tree [1]. The board code in turn derives from
>      the ARM sunxi board code, so its copyright notices are kept.
> 
>      [1] https://github.com/smaeul/u-boot/tree/d1-wip
> 
> 4/10 sunxi: dram: fix integer-pointer conversions in the D1 DRAM driver
>      Fix readl()/writel() address types for GCC 15+
> 
>      Use typed base address macros and cast remaining register addresses
>      to void __iomem * to satisfy GCC 15's stricter type checking.
> 
>      No functional change.
> 
> 5/10 sunxi: dram: count the banks on address bit 11, not A22
>      The bank test looks for the BA2 alias at address bit 22, but in the mode
>      the probe programs BA2 is bit 11. A four bank part therefore always
>      reports eight banks, turning 64MB into 128MB.
> 
>      On a MangoPi MQ with F133-A the probe now reports 4 banks, 13 rows and 2KB
>      pages - the vendor's dram_para1 = 0xd2. Boot tested on a Lichee RV Dock
>      too, where a D1 with external 512MB DDR3 is detected correctly.
> 
> 6/10 sunxi: dram: no AC remapping on the co-packaged DRAM parts
>      The PHY AC remapping tables compensate for the drive strength of the
>      DRAM chips connected to the SoC. This compensation must be skipped
>      when the DRAM is integrated on-die.
> 
> 7/10 sunxi: dram: let the board set the MR1 mode register
>      The DRAM mode register 1 value belongs to the DRAM part, and the parts in
>      use differ: 0x02 for the DDR2 die co-packaged with the D1s and F133-A,
>      against the 0x42 that the boards with external DDR3 have booted with so
>      far.
> 
>      Expose it next to the other vendor DRAM settings, keeping 0x42 as the
>      default so nothing changes for the existing users.
> 
> 8/10 sunxi: mmc: handle D1 PLL6 clock rate correctly
>      Apply the existing MMC clock /2 compensation to SUN20I,
>      as already done for SUN8I_R528.
> 
> 9/10 configs: add the Lichee RV Dock defconfig
>      Sipeed Lichee RV Dock: D1, 512 MB DDR3.
> 
> 10/10 configs: add the MangoPi MQ D1s(F133) defconfig
>      MangoPi MQ D1s(F133), 64 MB co-packaged DDR2.
> 
> 
>  MAINTAINERS                                   |  10 +
>  arch/riscv/Kconfig                            |  14 +
>  arch/riscv/cpu/sun20i/Kconfig                 |  17 +
>  arch/riscv/cpu/sun20i/Makefile                |   5 +
>  arch/riscv/cpu/sun20i/cache.c                 |  88 ++++
>  arch/riscv/cpu/sun20i/cpu.c                   |  44 ++
>  arch/riscv/cpu/sun20i/dram.c                  |  21 +
>  arch/riscv/dts/sun20i-u-boot.dtsi             |  86 ++++
>  arch/riscv/include/asm/arch-sun20i/clock.h    |  71 +++
>  arch/riscv/include/asm/arch-sun20i/cpu.h      |  22 +
>  .../riscv/include/asm/arch-sun20i/thead_csr.h |  29 ++
>  board/sun20i/Kconfig                          | 173 ++++++++
>  board/sun20i/Makefile                         |   4 +
>  board/sun20i/board.c                          | 309 +++++++++++++
>  board/sun20i/spl.c                            | 142 ++++++
>  configs/lichee_rv_dock_defconfig              |  14 +
>  configs/mangopi_mq_d1s_defconfig              |  20 +
>  drivers/clk/sunxi/Kconfig                     |   2 +-
>  drivers/gpio/Kconfig                          |   2 +-
>  drivers/mmc/Kconfig                           |   2 +-
>  drivers/mmc/sunxi_mmc.c                       |   3 +-
>  drivers/pinctrl/sunxi/Kconfig                 |   2 +-
>  drivers/ram/sunxi/Kconfig                     |   8 +-
>  drivers/ram/sunxi/dram_sun20i_d1.c            | 417 ++++++++++--------
>  drivers/reset/Kconfig                         |   2 +-
>  drivers/watchdog/Kconfig                      |   3 +-
>  include/configs/sun20i.h                      |  11 +
>  scripts/Makefile.xpl                          |   2 +-
>  28 files changed, 1329 insertions(+), 194 deletions(-)
>  create mode 100644 arch/riscv/cpu/sun20i/Kconfig
>  create mode 100644 arch/riscv/cpu/sun20i/Makefile
>  create mode 100644 arch/riscv/cpu/sun20i/cache.c
>  create mode 100644 arch/riscv/cpu/sun20i/cpu.c
>  create mode 100644 arch/riscv/cpu/sun20i/dram.c
>  create mode 100644 arch/riscv/dts/sun20i-u-boot.dtsi
>  create mode 100644 arch/riscv/include/asm/arch-sun20i/clock.h
>  create mode 100644 arch/riscv/include/asm/arch-sun20i/cpu.h
>  create mode 100644 arch/riscv/include/asm/arch-sun20i/thead_csr.h
>  create mode 100644 board/sun20i/Kconfig
>  create mode 100644 board/sun20i/Makefile
>  create mode 100644 board/sun20i/board.c
>  create mode 100644 board/sun20i/spl.c
>  create mode 100644 configs/lichee_rv_dock_defconfig
>  create mode 100644 configs/mangopi_mq_d1s_defconfig
>  create mode 100644 include/configs/sun20i.h
> 
> Cc
> --
> 
>   Tom Rini <trini@konsulko.com>               (U-Boot maintainer)
>   Andre Przywara <andre.przywara@arm.com>     (sunxi custodian)
>   Tim Ouyang <tim609@andestech.com>           (RISC-V)
>   Leo Liang <leo.liang@sifive.com>            (RISC-V)
>   Yao Zi <me@ziyao.cc>                        (RISC-V reviewer)
>   Peng Fan <peng.fan@nxp.com>                 (MMC)
>   Jaehoon Chung <jh80.chung@samsung.com>      (MMC)
>   Lukasz Majewski <lukma@nabladev.com>        (CLOCK)
>   Stefan Roese <stefan.roese@mailbox.org>     (WATCHDOG)
>   Samuel Holland <samuel@sholland.org>        (original d1-wip author)
>