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Fri, 06 Nov 2026 18:12:07 -0800 (PST) Received: from DESKTOP-NM9EKIA ([125.134.240.130]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36fa9be7077sm10949924eec.17.2026.11.06.18.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 18:12:06 -0800 (PST) From: Joonhoe Kim <26rote@gmail.com> To: Krzysztof Kozlowski Cc: Greg Kroah-Hartman , Thinh Nguyen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Wesley Cheng , Krishna Kurapati , Konrad Dybcio , Dmitry Baryshkov , Neil Armstrong , Val Packett , Balaji Kalkonda , Vladyslav Tymoshchuk , linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/3] dt-bindings: usb: qcom,snps-dwc3: Add mode-switch Date: Sat, 7 Nov 2026 11:12:08 +0900 Message-ID: <20261107021208.934-1-26rote@gmail.com> X-Mailer: git-send-email 2.55.0.windows.5 In-Reply-To: <20261104-bipedal-supportive-earwig-2aae26@quoll> References: <20261103135057.1682-1-26rote@gmail.com> <20261103135057.1682-2-26rote@gmail.com> <20261104-bipedal-supportive-earwig-2aae26@quoll> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Wed, Nov 04, 2026 at 02:13:21PM +0100, Krzysztof Kozlowski wrote: > On Tue, Nov 03, 2026 at 10:50:55PM +0900, Joonhoe Kim wrote: > > The QMP USB3-DP combo PHY stops the USB3 PIPE clock when a Type-C > > DisplayPort pin assignment gives it all four lanes for DisplayPort, > > while the controller can keep running its USB 2.0 port. The controller > > has to move to the UTMI clock before that happens, so it needs the > > Type-C mux state as well. fwnode_typec_mux_get() only matches graph > > Controller does not perform the switch, does it? No, it does not route any signals. It only needs to know the mode: in pin assignments C and E it selects the UTMI clock as its PIPE clock before the PHY stops the PIPE clock. usb-switch.yaml describes mode-switch as "Possible handler of altmode switching". The WCD939x codec uses it in a similar way: its mux callback only reports the audio accessory mode to its headset detection. The codec nodes in sm8650-qrd.dts and sm8750-mtp.dts have mode-switch. > > nodes that have the "mode-switch" property, so allow it on the > > controller node. > > So judging by this, you would need to fix fwnode_typec_mux_get() or > opther driver code, not the binding? The binding is needed because typec_mux_match() checks this property before the mux driver has probed (see the comment in typec_mux_match(), drivers/usb/typec/mux.c). Without that check, any graph neighbour that is not a mux would make fwnode_typec_mux_get() return -EPROBE_DEFER forever. Apple and Rockchip handle this in the PHY driver, because there the PHY driver can reach the controller-side USB3 control (the Apple PIPE handler, the Rockchip USB GRF). On Qualcomm the clock select is in the dwc3 glue (QSCRATCH), so the alternative would be a new interface for the QMP PHY to notify the controller. I found no existing one. It would have one advantage: the PHY knows when it actually switches. I can try that if you prefer it. > > + mode-switch: true > > Drop, but you might explicitly disallow orientation and retimer, if > entire solution stays after review. OK. v3 will keep the usb-switch.yaml reference, drop this line and set orientation-switch and retimer-switch to false. Thanks, Joonhoe Kim