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Sat, 07 Nov 2026 06:24:55 -0800 (PST) Received: from OpenwrtBuild.lan ([178.207.14.215]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3acf60c9cf4sm7125971fa.36.2026.11.07.06.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Nov 2026 06:24:55 -0800 (PST) From: Mikhail Zhilkin To: u-boot@lists.u-boot-project.org Cc: jerome.forissier@arm.com, ryder.lee@mediatek.com, weijie.gao@mediatek.com, chunfeng.yun@mediatek.com, igor.belwon@mentallysanemainliners.org, dlechner@baylibre.com, jstephan@baylibre.com, GSS_MTK_Uboot_upstream@mediatek.com, trini@konsulko.com, Mikhail Zhilkin Subject: [PATCH v1 0/3] net: mtk_eth: an8855: fix packet loss and sync with Linux Date: Sat, 7 Nov 2026 17:24:37 +0300 Message-ID: <20261107142441.2104669-1-csharper2005@gmail.com> X-Mailer: git-send-email 2.53.0 X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Sat, 07 Nov 2026 14:33:29 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_GMAIL_RCVD, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 This patch series aligns the U-Boot Airoha AN8855 switch initialization code with the upstream Linux DSA driver (drivers/net/dsa/airoha/an8855.c), fixing several register configuration bugs and improving overall signal integrity. The current default U-Boot configuration leaves the SerDes with marginal drive characteristics. On some hardware iterations, this results in severe packet loss (50-60%) and timeouts during TFTP recovery. This drop occurs because of marginal signal integrity on the internal 2500Base-X link connecting the switch to the CPU. By correcting a bitwise shift overlap, enabling link error recovery, and applying the proper TX FIR / RX CDR analog tuning parameters used in Linux, this series ensures a stable physical link between the CPU and switch across different boards. These changes have been run-tested on the CMCC RAX3000ME and Xiaomi AX3000T, both featuring the AN8855 switch, confirming stable network operation and reliable gigabit TFTP recovery. Patch summary: - Patch 1 fixes a bitwise collision bug in the AN8855_RX_CTRL_8 register that was accidentally overwriting previously set bits. - Patch 2 enables graceful link error recovery in AN8855_RX_CTRL_26 instead of explicitly disabling it. - Patch 3 ports the SerDes analog tuning parameters (TX Eye and RX Jitter Tolerance) from Linux, resolving the packet loss issue on the internal 2.5G CPU port. Mikhail Zhilkin (3): net: mtk_eth: an8855: fix bitwise collision in RX_CTRL_8 register net: mtk_eth: an8855: enable link error recovery net: mtk_eth: an8855: sync SerDes analog tuning with Linux driver drivers/net/mtk_eth/an8855.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) -- 2.53.0