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Sat, 07 Nov 2026 06:24:57 -0800 (PST) Received: from OpenwrtBuild.lan ([178.207.14.215]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3acf60c9cf4sm7125971fa.36.2026.11.07.06.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Nov 2026 06:24:56 -0800 (PST) From: Mikhail Zhilkin To: u-boot@lists.u-boot-project.org Cc: jerome.forissier@arm.com, ryder.lee@mediatek.com, weijie.gao@mediatek.com, chunfeng.yun@mediatek.com, igor.belwon@mentallysanemainliners.org, dlechner@baylibre.com, jstephan@baylibre.com, GSS_MTK_Uboot_upstream@mediatek.com, trini@konsulko.com, Mikhail Zhilkin Subject: [PATCH v1 1/3] net: mtk_eth: an8855: fix bitwise collision in RX_CTRL_8 register Date: Sat, 7 Nov 2026 17:24:38 +0300 Message-ID: <20261107142441.2104669-2-csharper2005@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261107142441.2104669-1-csharper2005@gmail.com> References: <20261107142441.2104669-1-csharper2005@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Sat, 07 Nov 2026 14:33:29 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-14.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_GMAIL_RCVD, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 In an8855_port_sgmii_init(), the bitwise operations for the AN8855_RX_CTRL_8 register contain a shifting error. The code attempts to set a value at shift 16 (0x200 << 16), but subsequently applies a mask and value shifted by 14 (0xfff << 14). This creates a bitwise collision where the second operation overlaps and overwrites the bits configured by the first operation, resulting in unintended register values. Fix the shift offset for the lower bits from 14 to 0 to prevent overlap and correctly apply the exact values used in the upstream Linux driver. Signed-off-by: Mikhail Zhilkin --- drivers/net/mtk_eth/an8855.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c index a2589a2ad31..eb037ec1382 100644 --- a/drivers/net/mtk_eth/an8855.c +++ b/drivers/net/mtk_eth/an8855.c @@ -627,8 +627,8 @@ static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port) an8855_reg_read(priv, AN8855_RX_CTRL_8, &val); val &= ~(0xfff << 16); val |= (0x200 << 16); - val &= ~(0x7fff << 14); - val |= (0xfff << 14); + val &= ~(0x7fff << 0); + val |= (0xfff << 0); an8855_reg_write(priv, AN8855_RX_CTRL_8, val); /* Frequency memter */ -- 2.53.0