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Sun, 08 Nov 2026 14:35:56 -0800 (PST) Received: from buildhost.darklands.se ([2001:9b1:ff:d701:51eb:176f:63d9:53f8]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b721ebc7b0sm859272a12.14.2026.11.08.14.35.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 14:35:55 -0800 (PST) From: Magnus Lindholm To: davem@davemloft.net, andreas@gaisler.com Cc: sparclinux@vger.kernel.org, linux-kernel@vger.kernel.org, linmag7@gmail.com Subject: [PATCH 0/9] sparc32: repair cache hooks, mappings and TLB tracking Date: Sun, 8 Nov 2026 23:34:10 +0100 Message-ID: <20261108223516.1125534-1-linmag7@gmail.com> X-Mailer: git-send-email 2.53.0 X-Mailing-List: sparclinux@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit I am submitting nine fixes for SPARC32 cache geometry, user-page copying, folio and anonymous-page maintenance, kmap PTEs and CPU-mask tracking. They apply to linux-sparc for-next at the base commit recorded below and apply independently of my separately posted bit-lock fix. Since summer 2026, I have been working on getting Linux to boot and run reliably on an SMP HyperSPARC SPARCstation 20, with native GDB builds as my main workload. That work exposed problems in both the HyperSPARC backends and the common SPARC32 cache and memory-management code. I am submitting the common SPARC32 fixes first because they address architecture-wide hooks and bookkeeping rather than HyperSPARC-specific backends. Some symptoms were exposed by HyperSPARC's cache behaviour, but the affected paths are shared with other SPARC32 processors. I plan to submit the HyperSPARC-specific fixes separately on top of this series. The SuperSPARC demap serialization change is a separate companion. Both application orders produce the same source tree; neither change narrows mm_cpumask. HyperSPARC-specific fixes and optimizations are not included. I completed a native GDB 18.1 build on a dual-CPU HyperSPARC RT626 SPARCstation 20 with 512 MB RAM, using a native SPARC32 SMP kernel with the combined fixes, optimizations and separate platform prerequisites. I observed no core dumps, livelock or new kernel messages. This was integration testing before this context-only rebase, not isolated testing of these nine patches. Individual patch test details are retained. For this rebase, SMP and UP builds and QEMU SS-20 fork/COW smoke tests passed both with and without the Viking companion. Validation builds included the separate PIL and IPI fixes, which are not in this series. Codex assisted with the rebase, review, validation and cover-letter preparation. Magnus Lindholm (9): sparc32: inspect every PROM CPU cache geometry sparc32: flush the source user alias in copy_user_highpage() sparc32: do not flush a NULL address in flush_dcache_folio sparc32: flush the cache when a kmap_local mapping is installed sparc32: preset modified and referenced bits in kmap PTEs sparc32: colour-align private file mappings sparc32: implement flush_anon_page sparc32: retain mm_cpumask across TLB shootdowns sparc32: enroll and order CPUs before switching address spaces arch/sparc/include/asm/cacheflush_32.h | 6 +++ arch/sparc/include/asm/highmem.h | 21 +++++++--- arch/sparc/include/asm/page_32.h | 6 +++ arch/sparc/include/asm/switch_to_32.h | 1 - arch/sparc/kernel/sys_sparc_32.c | 17 +++++++- arch/sparc/mm/init_32.c | 44 ++++++++++++++++++++ arch/sparc/mm/srmmu.c | 56 ++++++++++++++++++++------ 7 files changed, 130 insertions(+), 21 deletions(-) base-commit: a9e88d617a25306fa7e532b0b8be08df778872cc -- 2.43.0