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BCC: lkp@intel.com CC: oe-kbuild-all@lists.linux.dev TO: Olivier Louvignes CC: Jonathan Cameron CC: Joshua Crofts CC: Andy Shevchenko tree: https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git testing head: b70566610b48ba49dec636019da4d696db64b085 commit: 6abd2c32aed66a36992c2c0bdb45cf82bf5e42df [196/247] iio: adc: Add a driver for the Ingenic X1600 ADC :::::: branch date: 17 hours ago :::::: commit date: 2 days ago config: xtensa-randconfig-2200-20261109 (https://download.01.org/0day-ci/archive/20261109/202611091401.bBwOPdXb-lkp@intel.com/config) compiler: xtensa-linux-gcc (GCC) 8.5.0 smatch: v0.5.0-9187-g5189e3fb If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Reported-by: Dan Carpenter | Closes: https://lore.kernel.org/r/202611091401.bBwOPdXb-lkp@intel.com/ smatch warnings: drivers/iio/adc/ingenic-x1600-adc.c:119 x1600_adc_read_raw_channel() warn: subtract is higher precedence than shift drivers/iio/adc/ingenic-x1600-adc.c:119 x1600_adc_read_raw_channel() warn: subtract is higher precedence than shift drivers/iio/adc/ingenic-x1600-adc.c:119 x1600_adc_read_raw_channel() warn: subtract is higher precedence than shift drivers/iio/adc/ingenic-x1600-adc.c:119 x1600_adc_read_raw_channel() warn: subtract is higher precedence than shift vim +119 drivers/iio/adc/ingenic-x1600-adc.c 6abd2c32aed66a Olivier Louvignes 2026-11-06 91 6abd2c32aed66a Olivier Louvignes 2026-11-06 92 static int x1600_adc_read_raw_channel(struct x1600_adc *adc, unsigned int ch, int *val) 6abd2c32aed66a Olivier Louvignes 2026-11-06 93 { 6abd2c32aed66a Olivier Louvignes 2026-11-06 94 unsigned int bank, shift; 6abd2c32aed66a Olivier Louvignes 2026-11-06 95 u32 enable, data; 6abd2c32aed66a Olivier Louvignes 2026-11-06 96 int ret; 6abd2c32aed66a Olivier Louvignes 2026-11-06 97 6abd2c32aed66a Olivier Louvignes 2026-11-06 98 guard(mutex)(&adc->lock); 6abd2c32aed66a Olivier Louvignes 2026-11-06 99 6abd2c32aed66a Olivier Louvignes 2026-11-06 100 reinit_completion(&adc->done); 6abd2c32aed66a Olivier Louvignes 2026-11-06 101 x1600_adc_write(adc, X1600_ADC_REG_STATUS, BIT(ch)); 6abd2c32aed66a Olivier Louvignes 2026-11-06 102 enable = x1600_adc_read(adc, X1600_ADC_REG_ENABLE); 6abd2c32aed66a Olivier Louvignes 2026-11-06 103 x1600_adc_write(adc, X1600_ADC_REG_ENABLE, enable | BIT(ch)); 6abd2c32aed66a Olivier Louvignes 2026-11-06 104 6abd2c32aed66a Olivier Louvignes 2026-11-06 105 if (wait_for_completion_timeout(&adc->done, X1600_ADC_TIMEOUT)) 6abd2c32aed66a Olivier Louvignes 2026-11-06 106 ret = 0; 6abd2c32aed66a Olivier Louvignes 2026-11-06 107 else 6abd2c32aed66a Olivier Louvignes 2026-11-06 108 ret = -ETIMEDOUT; 6abd2c32aed66a Olivier Louvignes 2026-11-06 109 6abd2c32aed66a Olivier Louvignes 2026-11-06 110 enable = x1600_adc_read(adc, X1600_ADC_REG_ENABLE); 6abd2c32aed66a Olivier Louvignes 2026-11-06 111 x1600_adc_write(adc, X1600_ADC_REG_ENABLE, enable & ~BIT(ch)); 6abd2c32aed66a Olivier Louvignes 2026-11-06 112 if (ret) 6abd2c32aed66a Olivier Louvignes 2026-11-06 113 return ret; 6abd2c32aed66a Olivier Louvignes 2026-11-06 114 6abd2c32aed66a Olivier Louvignes 2026-11-06 115 /* Two results to a data register, the even channel's in the low half. */ 6abd2c32aed66a Olivier Louvignes 2026-11-06 116 bank = ch / 2; 6abd2c32aed66a Olivier Louvignes 2026-11-06 117 shift = ch % 2; 6abd2c32aed66a Olivier Louvignes 2026-11-06 118 data = x1600_adc_read(adc, X1600_ADC_REG_DATA(bank)); 6abd2c32aed66a Olivier Louvignes 2026-11-06 @119 *val = field_get(X1600_ADC_DATA_MASK(shift), data); 6abd2c32aed66a Olivier Louvignes 2026-11-06 120 6abd2c32aed66a Olivier Louvignes 2026-11-06 121 return 0; 6abd2c32aed66a Olivier Louvignes 2026-11-06 122 } 6abd2c32aed66a Olivier Louvignes 2026-11-06 123 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki