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Tue, 10 Nov 2026 08:29:19 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Kane Chen , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee , =?iso-8859-1?Q?C=E9dric_Le_Goater?= Subject: [PATCH v3 01/12] hw/usb/aspeed-udc: Make the SETUP buffer byte addressable Thread-Topic: [PATCH v3 01/12] hw/usb/aspeed-udc: Make the SETUP buffer byte addressable Thread-Index: AQHdcO2Ulzo3bXLcEUKdznnHNY1cLw== Date: Tue, 10 Nov 2026 08:29:19 +0000 Message-ID: <20261110082917.240329-2-jamin_lin@aspeedtech.com> References: <20261110082917.240329-1-jamin_lin@aspeedtech.com> In-Reply-To: <20261110082917.240329-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SEZPR06MB7362:EE_|SEYPR06MB5490:EE_ x-ms-office365-filtering-correlation-id: 64b6eb3d-0ad3-42af-fb1e-08df3f04b72e x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Archived-By: MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SEZPR06MB7362.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 64b6eb3d-0ad3-42af-fb1e-08df3f04b72e X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Nov 2026 08:29:19.5506 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: E2xYeuCRnL1NEnr8dFkblQnqA816RnyeAU24EK/M4Ewdd5M5vzeVs5skzMY+ir9LGxJLqG0kusuqiyZddqMnIiUkBvt6d0p2G28FPpTp2vs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEYPR06MB5490 Received-SPF: pass client-ip=2a01:111:f403:c40f::6; envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The controller registers need a 4 byte access, but the 8 bytes at 0x80=0A= are not registers. They are a SRAM buffer holding the EP0 SETUP packet.=0A= A read or a write that is not 4 bytes returned the wrong data, so the=0A= driver saw a broken SETUP packet.=0A= =0A= Introduce a separate SETUP MMIO region that handles 1, 2 and 4 byte=0A= reads and writes.=0A= =0A= Signed-off-by: Jamin Lin =0A= Reviewed-by: C=E9dric Le Goater =0A= ---=0A= include/hw/usb/aspeed-udc.h | 11 ++++++--=0A= hw/usb/aspeed-udc.c | 56 +++++++++++++++++++++++++++++++++----=0A= hw/usb/trace-events | 2 ++=0A= 3 files changed, 61 insertions(+), 8 deletions(-)=0A= =0A= diff --git a/include/hw/usb/aspeed-udc.h b/include/hw/usb/aspeed-udc.h=0A= index 7701c1aa34..42916c0bd6 100644=0A= --- a/include/hw/usb/aspeed-udc.h=0A= +++ b/include/hw/usb/aspeed-udc.h=0A= @@ -24,11 +24,14 @@ OBJECT_DECLARE_SIMPLE_TYPE(AspeedUDCState, ASPEED_UDC)= =0A= OBJECT_DECLARE_SIMPLE_TYPE(AspeedUDCGadget, ASPEED_UDC_GADGET)=0A= =0A= /*=0A= - * Register map: root/global block at 0x000 - 0x087, then one 0x10 byte ba= nk=0A= - * per programmable endpoint from 0x200.=0A= + * Register map: root/global block at 0x000 - 0x07f, the SETUP buffer at= =0A= + * 0x080 - 0x087, then one 0x10 byte bank per programmable endpoint from= =0A= + * 0x200.=0A= */=0A= #define ASPEED_UDC_MEM_SIZE 0x300=0A= -#define ASPEED_UDC_ROOT_NR_REGS (0x88 >> 2)=0A= +#define ASPEED_UDC_ROOT_NR_REGS (0x80 >> 2)=0A= +#define ASPEED_UDC_SETUP_BASE 0x80=0A= +#define ASPEED_UDC_SETUP_SIZE 0x08=0A= #define ASPEED_UDC_EP_REG_BASE 0x200=0A= #define ASPEED_UDC_EP_NR_REGS (0x10 >> 2)=0A= =0A= @@ -62,9 +65,11 @@ struct AspeedUDCState {=0A= =0A= MemoryRegion udc_container;=0A= MemoryRegion root_mr;=0A= + MemoryRegion setup_mr;=0A= MemoryRegion *dram_mr;=0A= AddressSpace dram_as;=0A= uint32_t regs[ASPEED_UDC_ROOT_NR_REGS];=0A= + uint8_t setup_buf[ASPEED_UDC_SETUP_SIZE];=0A= AspeedUDCEP ep[ASPEED_UDC_NUM_EP];=0A= qemu_irq irq;=0A= =0A= diff --git a/hw/usb/aspeed-udc.c b/hw/usb/aspeed-udc.c=0A= index 4c90b4f4c2..355512822b 100644=0A= --- a/hw/usb/aspeed-udc.c=0A= +++ b/hw/usb/aspeed-udc.c=0A= @@ -58,9 +58,6 @@ REG32(UDC_EP0_CTRL, 0x30)=0A= FIELD(UDC_EP0_CTRL, STALL, 0, 1)=0A= REG32(UDC_EP0_DATA_BUFF, 0x34)=0A= FIELD(UDC_EP0_DATA_BUFF, BASE_ADDR, 0, 31)=0A= -/* EP0 SETUP packet buffer: SETUP0 =3D bytes 0...3, SETUP1 =3D bytes 4...7= */=0A= -REG32(UDC_SETUP0, 0x80)=0A= -REG32(UDC_SETUP1, 0x84)=0A= =0A= /* Per programmable-endpoint registers (offset from the EP register base) = */=0A= REG32(EP_CONFIG, 0x00)=0A= @@ -363,6 +360,45 @@ static const MemoryRegionOps aspeed_udc_ops =3D {=0A= },=0A= };=0A= =0A= +static uint64_t aspeed_udc_setup_read(void *opaque, hwaddr offset,=0A= + unsigned size)=0A= +{=0A= + AspeedUDCState *s =3D ASPEED_UDC(opaque);=0A= + uint64_t value =3D 0;=0A= + int i;=0A= +=0A= + for (i =3D 0; i < size; i++) {=0A= + value |=3D (uint64_t)s->setup_buf[offset + i] << (8 * i);=0A= + }=0A= +=0A= + trace_aspeed_udc_setup_read(offset, size, value);=0A= +=0A= + return value;=0A= +}=0A= +=0A= +static void aspeed_udc_setup_write(void *opaque, hwaddr offset,=0A= + uint64_t value, unsigned size)=0A= +{=0A= + AspeedUDCState *s =3D ASPEED_UDC(opaque);=0A= + int i;=0A= +=0A= + trace_aspeed_udc_setup_write(offset, size, value);=0A= +=0A= + for (i =3D 0; i < size; i++) {=0A= + s->setup_buf[offset + i] =3D value >> (8 * i);=0A= + }=0A= +}=0A= +=0A= +static const MemoryRegionOps aspeed_udc_setup_ops =3D {=0A= + .read =3D aspeed_udc_setup_read,=0A= + .write =3D aspeed_udc_setup_write,=0A= + .endianness =3D DEVICE_LITTLE_ENDIAN,=0A= + .valid =3D {=0A= + .min_access_size =3D 1,=0A= + .max_access_size =3D 4,=0A= + },=0A= +};=0A= +=0A= /*=0A= * Copy len bytes from guest memory at addr into the IN packet, going thro= ugh=0A= * a bounce buffer one buf-full at a time. Returns false on DMA failure.= =0A= @@ -708,6 +744,7 @@ static void aspeed_udc_reset_hold(Object *obj, ResetTyp= e type)=0A= int i;=0A= =0A= memset(s->regs, 0, sizeof(s->regs));=0A= + memset(s->setup_buf, 0, sizeof(s->setup_buf));=0A= for (i =3D 0; i < ASPEED_UDC_NUM_EP; i++) {=0A= memset(s->ep[i].regs, 0, sizeof(s->ep[i].regs));=0A= s->ep[i].pkt =3D NULL;=0A= @@ -754,6 +791,12 @@ static void aspeed_udc_realize(DeviceState *dev, Error= **errp)=0A= ASPEED_UDC_ROOT_NR_REGS << 2);=0A= memory_region_add_subregion(&s->udc_container, 0, &s->root_mr);=0A= =0A= + memory_region_init_io(&s->setup_mr, OBJECT(s), &aspeed_udc_setup_ops,= =0A= + s, TYPE_ASPEED_UDC ".setup",=0A= + ASPEED_UDC_SETUP_SIZE);=0A= + memory_region_add_subregion(&s->udc_container,=0A= + ASPEED_UDC_SETUP_BASE, &s->setup_mr);=0A= +=0A= /* Each programmable endpoint has its own register bank */=0A= for (i =3D 0; i < ASPEED_UDC_NUM_EP; i++) {=0A= g_autofree char *name =3D g_strdup_printf(TYPE_ASPEED_UDC ".ep%d",= i);=0A= @@ -918,8 +961,11 @@ static void aspeed_udc_gadget_handle_control(USBDevice= *udev, USBPacket *p,=0A= * Reconstruct the 8-byte SETUP packet into the SETUP data buffer wher= e=0A= * the guest gadget driver reads it from.=0A= */=0A= - s->regs[R_UDC_SETUP0] =3D type | (req << 8) | ((value & 0xffff) << 16)= ;=0A= - s->regs[R_UDC_SETUP1] =3D (index & 0xffff) | ((length & 0xffff) << 16)= ;=0A= + s->setup_buf[0] =3D type;=0A= + s->setup_buf[1] =3D req;=0A= + stw_le_p(&s->setup_buf[2], value);=0A= + stw_le_p(&s->setup_buf[4], index);=0A= + stw_le_p(&s->setup_buf[6], length);=0A= =0A= /* A new SETUP clears the EP0 STALL condition */=0A= s->regs[R_UDC_EP0_CTRL] &=3D ~R_UDC_EP0_CTRL_STALL_MASK;=0A= diff --git a/hw/usb/trace-events b/hw/usb/trace-events=0A= index 36a870689f..7a84786fd0 100644=0A= --- a/hw/usb/trace-events=0A= +++ b/hw/usb/trace-events=0A= @@ -381,6 +381,8 @@ canokey_unrealize(void)=0A= # aspeed-udc.c=0A= aspeed_udc_read(uint64_t offset, uint32_t value) "offset 0x%" PRIx64 " val= ue 0x%x"=0A= aspeed_udc_write(uint64_t offset, uint32_t value) "offset 0x%" PRIx64 " va= lue 0x%x"=0A= +aspeed_udc_setup_read(uint64_t offset, unsigned size, uint64_t value) "off= set 0x%" PRIx64 " size %u value 0x%" PRIx64=0A= +aspeed_udc_setup_write(uint64_t offset, unsigned size, uint64_t value) "of= fset 0x%" PRIx64 " size %u value 0x%" PRIx64=0A= aspeed_udc_ep_read(int ep, uint64_t offset, uint32_t value) "ep %d, offset= 0x%" PRIx64 " value 0x%x"=0A= aspeed_udc_ep_write(int ep, uint64_t offset, uint32_t value) "ep %d, offse= t 0x%" PRIx64 " value 0x%x"=0A= aspeed_udc_pullup(int on, int attached) "on %d, attached %d"=0A= -- =0A= 2.43.0=0A=