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Tue, 10 Nov 2026 08:29:25 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Kane Chen , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee , =?iso-8859-1?Q?C=E9dric_Le_Goater?= Subject: [PATCH v3 03/12] hw/usb/aspeed-udc: Mask the reserved bits on register writes Thread-Topic: [PATCH v3 03/12] hw/usb/aspeed-udc: Mask the reserved bits on register writes Thread-Index: AQHdcO2VRa30O60gv0SoyAqoQndtGA== Date: Tue, 10 Nov 2026 08:29:21 +0000 Message-ID: <20261110082917.240329-4-jamin_lin@aspeedtech.com> References: <20261110082917.240329-1-jamin_lin@aspeedtech.com> In-Reply-To: <20261110082917.240329-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SEZPR06MB7362:EE_|SEYPR06MB5490:EE_ x-ms-office365-filtering-correlation-id: ef1f1f80-f627-4d58-da07-08df3f04ba83 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Archived-By: MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SEZPR06MB7362.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ef1f1f80-f627-4d58-da07-08df3f04ba83 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Nov 2026 08:29:21.5678 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: egjWcvGmmL54cI7RrwlrY2Sgbaee/9eZsXo+QKewrY6Ood1n9yRb4ys7JAXOxC7jVnQmI+zdJVm8dTSaj2gfxg6r58n7cNFZCd7Uwr8ynWc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEYPR06MB5490 Received-SPF: pass client-ip=2a01:111:f403:c40f::6; envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Writes to the interrupt registers were not masked, so a guest could set=0A= a reserved bit and read it back. The hardware returns 0 for those.=0A= =0A= Mask each one to the bits the datasheet marks read/write:=0A= =0A= UDC_IER 17, 16, 8:6, 4:0=0A= UDC_ISR 8:6, 4:0=0A= UDC_EP_ACK_IER 3:0=0A= UDC_EP_NAK_IER 3:0=0A= UDC_EP_ACK_ISR 3:0=0A= UDC_EP_NAK_ISR 3:0=0A= =0A= UDC_ISR bits 17 and 16 summarise the endpoint pool. They are read only,=0A= so a write cannot clear them.=0A= =0A= Signed-off-by: Jamin Lin =0A= Reviewed-by: C=E9dric Le Goater =0A= ---=0A= hw/usb/aspeed-udc.c | 12 +++++++++++-=0A= 1 file changed, 11 insertions(+), 1 deletion(-)=0A= =0A= diff --git a/hw/usb/aspeed-udc.c b/hw/usb/aspeed-udc.c=0A= index 6a5d05ce1f..945940cc99 100644=0A= --- a/hw/usb/aspeed-udc.c=0A= +++ b/hw/usb/aspeed-udc.c=0A= @@ -329,14 +329,24 @@ static void aspeed_udc_write(void *opaque, hwaddr off= set, uint64_t data,=0A= s->regs[R_UDC_FUNC_CTRL] =3D val;=0A= break;=0A= case R_UDC_IER:=0A= + val &=3D 0x000301df;=0A= + s->regs[reg] =3D val;=0A= + aspeed_udc_update_irq(s);=0A= + break;=0A= + case R_UDC_ISR:=0A= + val &=3D 0x000001df;=0A= + s->regs[reg] &=3D ~val;=0A= + aspeed_udc_update_irq(s);=0A= + break;=0A= case R_UDC_EP_ACK_IER:=0A= case R_UDC_EP_NAK_IER:=0A= + val &=3D 0x0000000f;=0A= s->regs[reg] =3D val;=0A= aspeed_udc_update_irq(s);=0A= break;=0A= - case R_UDC_ISR:=0A= case R_UDC_EP_ACK_ISR:=0A= case R_UDC_EP_NAK_ISR:=0A= + val &=3D 0x0000000f;=0A= s->regs[reg] &=3D ~val;=0A= aspeed_udc_update_irq(s);=0A= break;=0A= -- =0A= 2.43.0=0A=