[PATCH 2/4] accel/tcg: compare large pages under the flush mask

[Tim <mdspan.github@gmail.com>]

tlb_flush_range_locked() flushes entries whose address matches the
range under @mask, the low @bits of the address.  Its large page
check, however, compares the range end with the recorded large page
in all bits.  If the large page was entered under an address that
differs from the flushed range above @bits, the check fails, and the
large page is not flushed.

Compare under @mask as well.  This matters for the x86 LAM emulation
in the next patch, which installs TLB entries under tagged addresses
and flushes every tagged alias on INVLPG of the untagged address with
tlb_flush_page_bits_by_mmuidx().

Signed-off-by: Tim <mdspan.github@gmail.com>
---
 accel/tcg/cputlb.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index dc83f3b..ad2a5aa 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -691,8 +691,10 @@ static void tlb_flush_range_locked(CPUState *cpu, int midx,
      * Check if we need to flush due to large pages.
      * Because large_page_mask contains all 1's from the msb,
      * we only need to test the end of the range.
+     * Compare under @mask, ignoring bits above @bits.
      */
-    if (((addr + len - 1) & d->large_page_mask) == d->large_page_addr) {
+    if (((addr + len - 1) & d->large_page_mask & mask) ==
+        (d->large_page_addr & mask)) {
         tlb_debug("forcing full flush midx %d ("
                   "%016" VADDR_PRIx "/%016" VADDR_PRIx ")\n",
                   midx, d->large_page_addr, d->large_page_mask);
-- 
2.47.3