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From: Stuart Summers <stuart.summers@intel.com>
Cc: intel-xe@lists.freedesktop.org, rodrigo.vivi@intel.com,
	matthew.brost@intel.com, matthew.d.roper@intel.com,
	fei.yang@intel.com, Stuart Summers <stuart.summers@intel.com>
Subject: [PATCH 09/11] drm/xe: Fall back to CPU copies when the tile cannot blit
Date: Tue, 10 Nov 2026 23:14:51 +0000	[thread overview]
Message-ID: <20261110231442.218721-22-stuart.summers@intel.com> (raw)
In-Reply-To: <20261110231442.218721-13-stuart.summers@intel.com>

xe_migrate_copy() and xe_migrate_clear() emit blitter commands, and the
copy engine they need lives on the primary GT.  A tile without one can
still run the migration context for page table updates, but it has no way
to move data.

On an integrated device this never comes up, since every move either ends
in ttm_bo_move_null() or needs no clear.  With VRAM it does, so let
xe_bo_move() hand the work to ttm_bo_move_memcpy(), which reaches VRAM
through the BAR mapping xe already sets up in xe_ttm_io_mem_reserve(),
and which covers the clear case by way of an unpopulated source.  The
pinned save and restore paths grow the same check, falling back to the
vmap and memcpy branch they already have.

Reads come back over PCIe uncached and are correspondingly slow, so this
is only meant to keep a media only device working, not to perform.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/xe/xe_bo.c      | 43 ++++++++++++++++++++++-----------
 drivers/gpu/drm/xe/xe_migrate.c | 16 ++++++++++++
 drivers/gpu/drm/xe/xe_migrate.h |  2 ++
 3 files changed, 47 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 42a6aa1a2e4a..49a3d4df77f6 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -1275,6 +1275,19 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
 		xe_pm_runtime_get_noresume(xe);
 	}
 
+	/*
+	 * A tile with no copy engine cannot blit, so move the data with the
+	 * CPU instead.  For VRAM that means going over the PCIe BAR, which is
+	 * slow, but a device with no graphics IP offers no alternative.
+	 * ttm_bo_move_memcpy() covers the clear case too, by way of an
+	 * unpopulated source.
+	 */
+	if (!xe_migrate_can_blit(migrate)) {
+		ret = ttm_bo_move_memcpy(ttm_bo, ctx, new_mem);
+		xe_pm_runtime_put(xe);
+		goto out;
+	}
+
 	/*
 	 * Attach CCS BBs before submitting the copy job below so a VF
 	 * migration racing the copy sees valid, up to date attach state.
@@ -1576,17 +1589,18 @@ int xe_bo_notifier_unprepare_pinned(struct xe_bo *bo)
 static int xe_bo_evict_pinned_copy(struct xe_bo *bo, struct xe_bo *backup)
 {
 	struct xe_device *xe = xe_bo_device(bo);
+	struct xe_migrate *migrate;
 	bool unmap = false;
 	int ret = 0;
 
-	if (xe_bo_is_user(bo) || (bo->flags & XE_BO_FLAG_PINNED_LATE_RESTORE)) {
-		struct xe_migrate *migrate;
-		struct dma_fence *fence;
+	if (bo->tile)
+		migrate = bo->tile->migrate;
+	else
+		migrate = mem_type_to_migrate(xe, bo->ttm.resource->mem_type);
 
-		if (bo->tile)
-			migrate = bo->tile->migrate;
-		else
-			migrate = mem_type_to_migrate(xe, bo->ttm.resource->mem_type);
+	if ((xe_bo_is_user(bo) || (bo->flags & XE_BO_FLAG_PINNED_LATE_RESTORE)) &&
+	    xe_migrate_can_blit(migrate)) {
+		struct dma_fence *fence;
 
 		xe_assert(xe, bo->ttm.base.resv == backup->ttm.base.resv);
 		ret = dma_resv_reserve_fences(bo->ttm.base.resv, 1);
@@ -1715,6 +1729,7 @@ int xe_bo_restore_pinned(struct xe_bo *bo)
 	};
 	struct xe_device *xe = ttm_to_xe_device(bo->ttm.bdev);
 	struct xe_bo *backup = bo->backup_obj;
+	struct xe_migrate *migrate;
 	bool unmap = false;
 	int ret;
 
@@ -1729,14 +1744,14 @@ int xe_bo_restore_pinned(struct xe_bo *bo)
 			goto out_unlock_bo;
 	}
 
-	if (xe_bo_is_user(bo) || (bo->flags & XE_BO_FLAG_PINNED_LATE_RESTORE)) {
-		struct xe_migrate *migrate;
-		struct dma_fence *fence;
+	if (bo->tile)
+		migrate = bo->tile->migrate;
+	else
+		migrate = mem_type_to_migrate(xe, bo->ttm.resource->mem_type);
 
-		if (bo->tile)
-			migrate = bo->tile->migrate;
-		else
-			migrate = mem_type_to_migrate(xe, bo->ttm.resource->mem_type);
+	if ((xe_bo_is_user(bo) || (bo->flags & XE_BO_FLAG_PINNED_LATE_RESTORE)) &&
+	    xe_migrate_can_blit(migrate)) {
+		struct dma_fence *fence;
 
 		ret = dma_resv_reserve_fences(bo->ttm.base.resv, 1);
 		if (ret)
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 754592c5cf88..c06f43fc9e4f 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -2093,6 +2093,22 @@ void xe_migrate_wait(struct xe_migrate *m)
 		dma_fence_wait(m->fence, false);
 }
 
+/**
+ * xe_migrate_can_blit() - Whether a migration context can issue blits
+ * @m: The migration context
+ *
+ * xe_migrate_copy() and xe_migrate_clear() emit blitter commands, which only
+ * the copy engine understands, and the copy engine lives on the primary GT.
+ * A tile without one can still update page tables, so its migration context
+ * is usable, but callers that want to move data have to do it themselves.
+ *
+ * Return: true if blit based copy and clear are available on @m.
+ */
+bool xe_migrate_can_blit(struct xe_migrate *m)
+{
+	return m->tile->primary_gt;
+}
+
 static u32 pte_update_cmd_size(u64 size)
 {
 	u32 num_dword;
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index 2e8be10fdb71..4230efcaffc6 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -91,6 +91,8 @@ struct xe_vm *xe_migrate_get_vm(struct xe_migrate *m);
 
 void xe_migrate_wait(struct xe_migrate *m);
 
+bool xe_migrate_can_blit(struct xe_migrate *m);
+
 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
 int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
 				 struct xe_bo *scratch_bo,
-- 
2.43.0


  parent reply	other threads:[~2026-11-10 23:15 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-10 23:14 [PATCH 00/11] Allow boot with only media GT Stuart Summers
2026-11-10 23:14 ` [PATCH 01/11] drm/xe: Detect each GMD_ID IP in a loop Stuart Summers
2026-11-10 23:14 ` [PATCH 02/11] drm/xe: Tolerate a missing graphics IP in xe_info_init() Stuart Summers
2026-11-10 23:14 ` [PATCH 03/11] drm/xe: Verify IP presence against GU_CNTL Stuart Summers
2026-11-10 23:14 ` [PATCH 04/11] drm/xe: Guard per-tile primary GT accesses Stuart Summers
2026-11-10 23:14 ` [PATCH 05/11] drm/xe: Stop assuming the root tile has a primary GT Stuart Summers
2026-11-11  2:59   ` sashiko-bot
2026-11-10 23:14 ` [PATCH 06/11] drm/xe: Do not claim flat CCS without a graphics IP Stuart Summers
2026-11-11  3:21   ` sashiko-bot
2026-11-10 23:14 ` [PATCH 07/11] drm/xe: Run page table updates on the media GT when there is no primary Stuart Summers
2026-11-11  3:53   ` sashiko-bot
2026-11-10 23:14 ` [PATCH 08/11] drm/xe: Document that gt_types_allowed=media now probes Stuart Summers
2026-11-10 23:14 ` Stuart Summers [this message]
2026-11-11  4:25   ` [PATCH 09/11] drm/xe: Fall back to CPU copies when the tile cannot blit sashiko-bot
2026-11-10 23:14 ` [PATCH 10/11] drm/xe: Require a fully visible VRAM BAR without a primary GT Stuart Summers
2026-11-11  4:38   ` sashiko-bot
2026-11-10 23:14 ` [PATCH 11/11] drm/xe: Allow probe " Stuart Summers
2026-11-11  4:57   ` sashiko-bot
2026-11-10 23:39 ` ✓ CI.KUnit: success for Allow boot with only media GT Patchwork
2026-11-11  0:14 ` ✓ Xe.CI.BAT: " Patchwork
2026-11-11  4:17 ` ✓ Xe.CI.FULL: " Patchwork
2026-11-12 12:21 ` [PATCH 00/11] " Piotr Piórkowski

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