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Tue, 10 Nov 2026 19:41:16 -0600 From: Wayne Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Alvin Lee , Wenjing Liu Subject: [PATCH 15/74] drm/amd/display: Update indicate pstate enable sequence Date: Wed, 11 Nov 2026 09:28:21 +0800 Message-ID: <20261111014100.3596072-16-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com> References: <20261111014100.3596072-1-Wayne.Lin@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="y" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231B:EE_|PH7PR12MB8107:EE_ X-MS-Office365-Filtering-Correlation-Id: 9a3d084c-1c74-4556-a999-08df3f94e57b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|23010399003|376014|1800799024|82310400026|36860700016|261026140227099003|261021123027099003|11063799006|261022105027099003|261021121427099003|56012099006|261009223027099003|261102123227099003|261028144727099003|10067099003|10063799003|18002099003|22082099003|3023799007; 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The other status bits must be correct from the start Cc: Wenjing Liu Signed-off-by: Alvin Lee Signed-off-by: Wayne Lin --- .../display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 35 +++++++------------ 1 file changed, 13 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c index 98d146bc25c0..4242a4b5c902 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c @@ -1370,6 +1370,7 @@ static void dcn60_make_bandwidth_clocks_update_action( * @block_sequence: output array of block sequence steps * @action: action struct populated by dcn60_make_bandwidth_clocks_update_action * @clk_mgr_base: current clock manager state (read-only, used for original values) + * @context: dc state with active plane information * @new_clocks: requested clock values for message parameters * * Return: number of steps written to block_sequence @@ -1378,9 +1379,11 @@ static unsigned int dcn60_build_bandwidth_clocks_block_sequence_with_action( struct dcn60_clk_mgr_block_sequence *block_sequence, struct dcn60_bandwidth_clocks_update_action *action, struct clk_mgr *clk_mgr_base, + struct dc_state *context, struct dc_clocks *new_clocks) { unsigned int num_steps = 0; + bool no_active_planes = clk_mgr_helper_get_active_plane_cnt(clk_mgr_base->ctx->dc, context) == 0; /* CLK_MGR60_INDICATE_PSTATE_STATUS — enable */ if ((action->uclk_pstate.enable && action->uclk_pstate.send_message) @@ -1394,14 +1397,11 @@ static unsigned int dcn60_build_bandwidth_clocks_block_sequence_with_action( action->fclk_pstate.enable || clk_mgr_base->clks.fclk_p_state_change_support; block_sequence[num_steps].params.indicate_pstate_status_params.drr_enable = - action->fams.enable - || clk_mgr_base->clks.fw_based_mclk_switching; - block_sequence[num_steps].params.indicate_pstate_status_params.wait_resp = - action->fams.enable - || clk_mgr_base->clks.fw_based_mclk_switching; + new_clocks->fw_based_mclk_switching; block_sequence[num_steps].params.indicate_pstate_status_params.alt_ch_enable = - action->alt_ch.enable - || clk_mgr_base->clks.alt_ch_pstate_switch; + new_clocks->alt_ch_pstate_switch; + block_sequence[num_steps].params.indicate_pstate_status_params.wait_resp = + new_clocks->fw_based_mclk_switching; block_sequence[num_steps].func = CLK_MGR60_INDICATE_PSTATE_STATUS; num_steps++; } @@ -1443,24 +1443,15 @@ static unsigned int dcn60_build_bandwidth_clocks_block_sequence_with_action( || (action->fams.disable && action->fams.send_message) || (action->alt_ch.disable && action->alt_ch.send_message)) { block_sequence[num_steps].params.indicate_pstate_status_params.allow_uclk = - !action->uclk_pstate.disable - && (action->uclk_pstate.enable - || clk_mgr_base->clks.p_state_change_support); + new_clocks->p_state_change_support || no_active_planes; block_sequence[num_steps].params.indicate_pstate_status_params.allow_fclk = - !action->fclk_pstate.disable - && (action->fclk_pstate.enable - || clk_mgr_base->clks.fclk_p_state_change_support); + new_clocks->fclk_p_state_change_support || no_active_planes; block_sequence[num_steps].params.indicate_pstate_status_params.drr_enable = - !action->fams.disable - && (action->fams.enable - || clk_mgr_base->clks.fw_based_mclk_switching); + new_clocks->fw_based_mclk_switching; block_sequence[num_steps].params.indicate_pstate_status_params.alt_ch_enable = - !action->alt_ch.disable - && (action->alt_ch.enable - || clk_mgr_base->clks.alt_ch_pstate_switch); + new_clocks->alt_ch_pstate_switch; block_sequence[num_steps].params.indicate_pstate_status_params.wait_resp = - action->fams.enable - || clk_mgr_base->clks.fw_based_mclk_switching; + new_clocks->fw_based_mclk_switching; block_sequence[num_steps].func = CLK_MGR60_INDICATE_PSTATE_STATUS; num_steps++; } @@ -1552,7 +1543,7 @@ static unsigned int dcn60_build_update_bandwidth_clocks_sequence( num_steps = dcn60_build_bandwidth_clocks_block_sequence_with_action( clk_mgr60->block_sequence, &action, - clk_mgr_base, new_clocks); + clk_mgr_base, context, new_clocks); dcn60_update_bandwidth_clocks_state_with_action(clk_mgr_base, &action, new_clocks); -- 2.43.0