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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9235 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Piotr Maziarz [WHY] The DCN401 clk_mgr DENTIST step keeps an unused dc_state pointer and, when it executes, reads the current DISPCLK from clk_mgr, the DENTIST VCO frequency and dc->debug.override_dispclk_programming to decide whether and how to program the divider. DCN60 still declares the same unused dc_state-carrying parameters. [HOW] Compute the DISPCLK divider when the sequence is built and store it in the step. Emit the step only when the debug override is set and DISPCLK is known, which is when the executor used to program anything; the executor keeps only the register read-back and update. Drop the unused DENTIST parameters from the DCN60 sequence. Cc: Alvin Lee Signed-off-by: Piotr Maziarz Signed-off-by: Wayne Lin --- .../dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 63 ++++++++++--------- .../dc/clk_mgr/dcn401/dcn401_clk_mgr.h | 2 +- .../display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h | 4 -- 3 files changed, 33 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 0785f70fb535..dccc9012c7fc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -548,33 +548,18 @@ static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mg static void dcn401_update_clocks_update_dentist( struct clk_mgr_internal *clk_mgr, - struct dc_state *context) + uint32_t new_dispclk_wdivider) { - (void)context; - uint32_t new_disp_divider = 0; - uint32_t new_dispclk_wdivider = 0; uint32_t dentist_dispclk_wdivider_readback = 0; - struct dc *dc = clk_mgr->base.ctx->dc; - - if (clk_mgr->base.clks.dispclk_khz == 0) - return; - - new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR - * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; - new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider); + REG_GET(DENTIST_DISPCLK_CNTL, + DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback); - if (dc->debug.override_dispclk_programming) { - REG_GET(DENTIST_DISPCLK_CNTL, - DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback); - - if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) { - REG_UPDATE(DENTIST_DISPCLK_CNTL, - DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider); - REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000); - } + if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) { + REG_UPDATE(DENTIST_DISPCLK_CNTL, + DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider); + REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000); } - } static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned int num_steps) @@ -678,7 +663,7 @@ static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned case CLK_MGR401_UPDATE_DENTIST: dcn401_update_clocks_update_dentist( clk_mgr_internal, - params->update_dentist_params.context); + params->update_dentist_params.dispclk_wdivider); break; case CLK_MGR401_UPDATE_PSR_WAIT_LOOP: params->update_psr_wait_loop_params.dmcu->funcs->set_psr_wait_loop( @@ -1009,6 +994,27 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( return num_steps; } +/* Outside the dispclk programming debug override, DENTIST is not reprogrammed here. */ +static unsigned int dcn401_add_update_dentist_step( + struct clk_mgr *clk_mgr_base, + struct dcn401_clk_mgr_block_sequence *block_sequence, + unsigned int num_steps) +{ + uint32_t new_disp_divider; + + if (!clk_mgr_base->ctx->dc->debug.override_dispclk_programming || + clk_mgr_base->clks.dispclk_khz == 0) + return num_steps; + + new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR + * clk_mgr_base->dentist_vco_freq_khz / clk_mgr_base->clks.dispclk_khz; + + block_sequence[num_steps].params.update_dentist_params.dispclk_wdivider = + dentist_get_did_from_divider(new_disp_divider); + block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST; + return num_steps + 1; +} + static unsigned int dcn401_build_update_display_clocks_sequence( struct clk_mgr *clk_mgr_base, struct dc_state *context, @@ -1119,9 +1125,7 @@ static unsigned int dcn401_build_update_display_clocks_sequence( block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO; num_steps++; - block_sequence[num_steps].params.update_dentist_params.context = context; - block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST; - num_steps++; + num_steps = dcn401_add_update_dentist_step(clk_mgr_base, block_sequence, num_steps); if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) { block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK; @@ -1146,11 +1150,8 @@ static unsigned int dcn401_build_update_display_clocks_sequence( num_steps++; } - if (update_dppclk || update_dispclk) { - block_sequence[num_steps].params.update_dentist_params.context = context; - block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST; - num_steps++; - } + if (update_dppclk || update_dispclk) + num_steps = dcn401_add_update_dentist_step(clk_mgr_base, block_sequence, num_steps); block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz; clk_mgr_build_dpp_dto_targets(dc, context, safe_to_lower, diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h index a2ba8b665a14..c87fb8e794a6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h @@ -61,7 +61,7 @@ union dcn401_clk_mgr_block_sequence_params { struct clk_mgr_dtbclk_dto_target update_dtbclk_dto_params; struct { /* inputs */ - struct dc_state *context; + uint32_t dispclk_wdivider; } update_dentist_params; struct { /* inputs */ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h index bd61817a5ef9..9f945d2eb78a 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h @@ -50,10 +50,6 @@ union dcn60_clk_mgr_block_sequence_params { struct clk_mgr_dpp_dto_targets targets; } update_dppclk_dto_params; struct clk_mgr_dtbclk_dto_target update_dtbclk_dto_params; - struct { - /* inputs */ - struct dc_state *context; - } update_dentist_params; struct { /* inputs */ struct dmcu *dmcu; -- 2.43.0