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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9517 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Dillon Varone [WHY&HOW] Cleanup unused tiling and address cases and improve version enum. Cc: Aric Cyr Signed-off-by: Dillon Varone Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 16 +++--- .../dc/dml2_wrapper/dml2_mall_phantom.c | 1 - .../amd/display/dc/hubp/dcn50/dcn50_hubp.c | 52 ++----------------- 3 files changed, 13 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index eb9effb22658..20504dfb1b13 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -390,14 +390,14 @@ enum swizzle_mode_addr3_values { DC_ADDR3_SW_UNKNOWN = DC_ADDR3_SW_MAX }; -enum dc_gfxversion { - DcGfxVersion7 = 0, - DcGfxVersion8, - DcGfxVersion9, - DcGfxVersion10, - DcGfxVersion11, - DcGfxAddr3, - DcGfxVersionUnknown +enum dc_gfx_addr_version { + DcGfxVersion7 = 0x0700, + DcGfxVersion8 = 0x0800, + DcGfxVersion9 = 0x0900, + DcGfxVersion10 = 0x0A00, + DcGfxVersion11 = 0x0B00, + DcGfxAddr3 = 0x0C00, + DcGfxVersionUnknown = 0xFFFF }; struct dc_tiling_info { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c index edc4dcdde952..bd2c2b82b176 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c @@ -808,7 +808,6 @@ static void enable_phantom_plane(struct dml2_context *ctx, memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, sizeof(phantom_plane->tiling_info)); memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); - //phantom_plane->tiling_info.gfx10compatible.compat_level = curr_pipe->plane_state->tiling_info.gfx10compatible.compat_level; phantom_plane->format = curr_pipe->plane_state->format; phantom_plane->rotation = curr_pipe->plane_state->rotation; phantom_plane->visible = curr_pipe->plane_state->visible; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.c index ba86e30b1180..ceea0b766f5b 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.c @@ -217,57 +217,15 @@ static void hubp50_program_tiling( const enum surface_pixel_format pixel_format) { (void)pixel_format; - /* Tiling address-generation compatibility level programmed into the - * DCSURF_TILING_CONFIG.COMPAT_LEVEL register field: - * 0 - gfx8 bank_height == 1 - * 1 - gfx8 bank_height == 2 - * 2 - gfx9/10/11 - * 5 - gfx addr3 - */ - unsigned int compat_level = 0; + enum swizzle_mode_values swizzle_mode; - switch (info->gfxversion) { - case DcGfxVersion7: - case DcGfxVersion8: - - REG_UPDATE_8(DCSURF_LEGACY_ADDR_CONFIG, - LEGACY_NUM_BANKS, info->gfx8.num_banks, - BANK_WIDTH, info->gfx8.bank_width, - BANK_HEIGHT, info->gfx8.bank_height, - MACRO_TILE_ASPECT, info->gfx8.tile_aspect, - TILE_SPLIT, info->gfx8.tile_split, - MICRO_TILE_MODE_NEW, info->gfx8.tile_mode, - PIPE_CONFIG, info->gfx8.pipe_config, - ARRAY_MODE, info->gfx8.array_mode); - if (info->gfx8.bank_height == 1) { - compat_level = 0; - } else if (info->gfx8.bank_height == 2) { - compat_level = 1; - } - break; - - case DcGfxVersion9: - case DcGfxVersion10: - case DcGfxVersion11: - REG_UPDATE_4(DCSURF_ADDR_CONFIG, - NUM_PIPES, log_2(info->gfx9.num_pipes), - PIPE_INTERLEAVE, info->gfx9.pipe_interleave, - MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags), - NUM_PKRS, log_2(info->gfx9.num_pkrs)); - REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx9.swizzle); - compat_level = 2; - - break; - case DcGfxAddr3: - swizzle_mode = hubp50_addr3_to_swizzle_mode_mapping(info->gfx_addr3.swizzle); - REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, swizzle_mode); - compat_level = 5; - break; - } + ASSERT(info->gfxversion == DcGfxAddr3); - REG_UPDATE(DCSURF_TILING_CONFIG, COMPAT_LEVEL, compat_level); + swizzle_mode = hubp50_addr3_to_swizzle_mode_mapping(info->gfx_addr3.swizzle); + REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, swizzle_mode); } + static void hubp50_program_pixel_format( struct hubp *hubp, enum surface_pixel_format format) -- 2.43.0